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Publication years (Num. hits)
1980-1985 (16) 1986-1988 (22) 1989-1990 (21) 1991 (15) 1992-1993 (29) 1994 (17) 1995 (69) 1996 (37) 1997 (31) 1998 (20) 1999 (28) 2000 (35) 2001 (25) 2002 (24) 2003 (22) 2004 (25) 2005 (23) 2006 (22) 2007 (16) 2008 (26) 2009-2011 (18) 2012-2014 (15) 2015-2019 (14)
Publication types (Num. hits)
article(208) inproceedings(360) phdthesis(2)
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Found 570 publication records. Showing 570 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
90Dong Xiang, Yi Xu, Hideo Fujiwara Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF inversion parity, nonscan design for testability, sequential depth for testability, Conflict, testability measure, partial scan design
84Indradeep Ghosh, Niraj K. Jha, Sujit Dey A low overhead design for testability and test generation technique for core-based systems-on-a-chip. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
77Frank F. Hsu, Janak H. Patel A distance reduction approach to design for testability. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques
73Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian Easily Testable Cellular Carry Lookahead Adders. Search on Bibsonomy J. Electronic Testing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model
68Alvin Jee, F. Joel Ferguson A methodolgy for characterizing cell testability. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF cell testability, stuck-at fault coverage, IC quality, physical design for testability, metric, integrated circuit design, integrated circuit design, DPM, manufacturing defects
67Dong Xiang, Shan Gu, Hideo Fujiwara Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
66Charles E. Stroud, Ahmed E. Barbour Testability and test generation for majority voting fault-tolerant circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1993 DBLP  DOI  BibTeX  RDF majority voting circuits, fault-tolerance, Design for testability, test pattern generation, multiple stuck-at faults
66Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Equivalent faults, One-port circuits, Fault diagnosis, Design for testability, Fault collapsing
60Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang Design-for-testability and fault-tolerant techniques for FFT processors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
59Dong Xiang, Shan Gu, Hideo Fujiwara Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
58H. S. Fung, S. Hirschhorn, R. Kulkarni Design for testability in a silicon compilation environment. Search on Bibsonomy DAC The full citation details ... 1985 DBLP  DOI  BibTeX  RDF
53Karim Arabi, Bozena Kaminska, Stephen K. Sunter Design for testability of integrated operational amplifiers using oscillation-test strategy. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF integrated operational amplifiers, oscillation-test strategy, vector-less test solution, test mode, oscillation frequency, nominal tolerance, digital circuitry, high fault coverage, simulation, design for testability, design for testability, oscillators, operational amplifiers, Monte Carlo analysis
52Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
51Amey Karkare, Manoj Singla, Ajai Jain Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Testability Preserving Transformations, Testability Enhancing Transformations, DFT, Testability, Delay Faults
50Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha A design-for-testability technique for register-transfer level circuits using control/data flow extraction. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
48Kee Sup Kim, Charles R. Kime Partial scan flip-flop selection by use of empirical testability. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF scan flip-flop selection, serial scan, design for testability, testability, partial scan
48Abhijit Chatterjee, Jacob A. Abraham Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. Search on Bibsonomy J. Electronic Testing The full citation details ... 1991 DBLP  DOI  BibTeX  RDF Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test
48Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
47Irith Pomeranz, Sudhakar M. Reddy Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF synchronization, design-for-testability, synchronous sequential circuits
47Frank F. Hsu, Janak H. Patel Design for Testability Using State Distances. Search on Bibsonomy J. Electronic Testing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF state distance, finite-state-machine, design-for-testability, synthesis-for-testability
44Thao Nguyen, Navid Rezvani Printed Circuit Board Assembly Test Process and Design for Testability. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
44Sujit Dey, Miodrag Potkonjak Nonscan design-for-testability techniques using RT-level design information. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
43Irith Pomeranz, Sudhakar M. Reddy Synthesis for Broadside Testability of Transition Faults. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF broadside tests, standard scan, transition faults, test synthesis, full-scan circuits
42Sandhya Seshadri, Michael S. Hsiao Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability. Search on Bibsonomy J. Electronic Testing The full citation details ... 2000 DBLP  DOI  BibTeX  RDF behavioral level, value range, SSA representation, design for testability
41Giacomo Buonanno, Franco Fummi, Donatella Sciuto TIES: A testability increase expert system for VLSI design. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF design for testability techniques, DfT advisor, testability analysis, testable design
41Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
41Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Hierarchical test generation and design for testability methods for ASPPs and ASIPs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
40Thomas W. Williams Design for Testability: The Path to Deep Submicron. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
40Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF strong testability, partially strong testability, complete fault efficiency, design-for-testability, data paths
40Tomokazu Yoneda, Hideo Fujiwara Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. Search on Bibsonomy J. Electronic Testing The full citation details ... 2002 DBLP  DOI  BibTeX  RDF consecutive transparency, built-in self test, design for testability, system-on-a-chip, test access mechanism, consecutive testability
40Tomokazu Yoneda, Hideo Fujiwara A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF consecutive transparency, core-based systems-on-a-chip, design for testability, test access mechanism, consecutive testability
40Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik Integration of partial scan and built-in self-test. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF test points, built-in self-test, design for testability, partial scan
40Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer On testable multipliers for fixed-width data path architectures. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Fixed-Width Architectures, Built-in Self -Test, High-level Synthesis, Design for Testability
40Seiken Yano Unified scan design with scannable memory arrays. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
39Da Wang, Yu Hu, Huawei Li, Xiaowei Li 0001 Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
39Teemu Kanstrén A Study on Design for Testability in Component-Based Embedded Software. Search on Bibsonomy SERA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF testing, components, design for testability, embedded software
39Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF core test, design-for-testability, BIST, scan, boundary scan, test bus
39Prab Varma, Tushar Gheewala The economics of scan-path design for testability. Search on Bibsonomy J. Electronic Testing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF state retention problem, Design for testability, scan, partial scan, test economics, life-cycle costs
39Shyue-Kung Lu, Chien-Hung Yeh Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. Search on Bibsonomy J. Electronic Testing The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Radio Frequency (RF) Testing, Design for Testability (DFT), Voltage Controlled Oscillator (VCOs)
38Cecilia Metra, T. M. Mak, Martin Omaña Fault secureness need for next generation high performance microprocessor design for testability structures. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF built in self test, design for testability, microprocessor, comparator, fault secureness
38Yervant Zorian Fundamentals of MCM Testing and Design-for-Testability. Search on Bibsonomy J. Electronic Testing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF known good dies, design-for-testability, MCM testing
38Michiel M. Ligthart, Emile H. L. Aarts, Frans P. M. Beenker Design-for-testability of PLA's using statistical cooling. Search on Bibsonomy DAC The full citation details ... 1986 DBLP  DOI  BibTeX  RDF PLA testing, statistical cooling, design-for-testability, PLA
38Roberto Bevacqua, Luca Guerrazzi, Franco Fummi SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
38Imtiaz P. Shaik, Michael L. Bushnell A graph approach to DFT hardware placement for robust delay fault BIST. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
38Elizabeth M. Rudnick, Janak H. Patel A genetic approach to test application time reduction for full scan and partial scan circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
38Mohamed Soufi, Yvon Savaria, Bozena Kaminska On the design of at-speed testable VLSI circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
38S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault Test configurations to enhance the testability of sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
35Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu Design of C-Testable Multipliers Based on the Modified Booth Algorithm. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model
35Arun Balakrishnan, Srimat T. Chakradhar Software transformations for sequential test generation. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF sequential test generation, high fault coverage test sets, testability properties, inverse mapping, software engineering, logic testing, timing, design for testability, sequential circuits, sequential circuits, DFT, software model, software transformations
34Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara A DFT Method for Time Expansion Model at Register Transfer Level. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Shyue-Kung Lu, Mau-Jung Lu Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Abhijit Chatterjee, Naveena Nagi Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
34Vivek Chickermane, Jaushin Lee, Janak H. Patel Addressing design for testability at the architectural level. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
33Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha A design for testability technique for RTL circuits using control/data flow extraction. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
33Sujit Dey, Vijay Gangaram, Miodrag Potkonjak A controller-based design-for-testability technique for controller-data path circuits. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
33Sujit Dey, Miodrag Potkonjak Non-scan design-for-testability of RT-level data paths. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
33Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet Test and Testability of a Monolithic MEMS for Magnetic Field Sensing. Search on Bibsonomy J. Electronic Testing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF design for testability, production testing, low-cost testing, MEMS testing
32Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
32Shaahin Hessabi, M. Y. Osman, Mohamed I. Elmasry Differential BiCMOS logic circuits: fault characterization and design-for-testability. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
32Richard M. Chou, Kewal K. Saluja Sequential Circuit Testing: From DFT to SFT. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques
30T. W. Williams Testing in Nanometer Technologies. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
29Jin-Fu Li, Cheng-Wen Wu Efficient FFT network testing and diagnosis schemes. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
29Rolf Drechsler, Junhao Shi, Görschwin Fey MuTaTe: an efficient design for testability technique for multiplexor based circuits. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multiplexor based circuits, design for testability, logic synthesis, BDDs, decision diagrams
29Yves Le Traon, Daniel Deveaux, Jean-Marc Jézéquel Self-Testable Components: From Pragmatic Tests to Design-for-Testability Methodology. Search on Bibsonomy TOOLS (29) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF testing, design-for-testability, self-test, design by contract, reusable components
29Sujit Dey, Anand Raghunathan, Kenneth D. Wagner Design for Testability Techniques at the Behavioral and Register-Transfer Levels. Search on Bibsonomy J. Electronic Testing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
29Saied Bozorgui-Nesbat, Edward J. McCluskey Lower Overhead Design for Testability of Programmable Logic Arrays. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1986 DBLP  DOI  BibTeX  RDF test generation for PLA's, PLA testing, Design for testability, programmable logic arrays (PLA)
29Dhruva R. Chakrabarti, Ajai Jain An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
29Franco Fummi, Donatella Sciuto, M. Serro Synthesis for testability of large complexity controllers. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates
28Matthew L. King, Kewal K. Saluja Testing Micropipelined Asynchronous Circuits. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
28Benoit Baudry, Yves Le Traon, Gerson Sunyé Testability Analysis of a UML Class Diagram. Search on Bibsonomy IEEE METRICS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
28João Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves A methodology for testability enhancement at layout level. Search on Bibsonomy J. Electronic Testing The full citation details ... 1991 DBLP  DOI  BibTeX  RDF physical design rules for testability, simulation, fault modeling, testability analysis
27Chia Yee Ooi, Hideo Fujiwara A New Design-for-Testability Method Based on Thru-Testability. Search on Bibsonomy J. Electronic Testing The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
27Dong Xiang, Yi Xu Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement. Search on Bibsonomy ICCD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
27Rachida Dssouli, Kamel Karoui, Kassem Saleh, Omar Cherkaoui Communications software design for testability: specification transformations and testability measures. Search on Bibsonomy Information & Software Technology The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
27Sandhya Seshadri, Michael S. Hsiao An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques. Search on Bibsonomy ITC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
27Ting-Hua Chen, Melvin A. Breuer Automatic Design for Testability Via Testability Measures. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1985 DBLP  DOI  BibTeX  RDF
27Anthony Chung, Tao Huang Two Approaches for the Improvement in Testability of Communication Protocols. Search on Bibsonomy ACIS-ICIS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. Search on Bibsonomy DSD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Nai-Chi Lee A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards. Search on Bibsonomy J. Electronic Testing The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
27João Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves, R. Crespo A strategy for testability enhancement at layout level. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
27Mehrdad Bidjan-Irani A Rule-Based Design-for-Testability Rule Checker. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
26Sunwoong Yang, MoonJoon Kim, JaeHeung Park, Hoon Chang A Study on Methodology for Enhancing Reliability of Datapath. Search on Bibsonomy ICCSA (1) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Shyue-Kung Lu, Chien-Hung Yeh Enhancing Delay Fault Testability for Iterative Logic Array. Search on Bibsonomy PRDC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
26Jacob Savir Design for Testability to Combat Delay Faults. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF BIST, LFSR, Delay Test, MISR, LSSD, SRL
26Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka A Design for testability Method Using RTL Partitioning. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF line-up structure, internally balanced structure, acyclic structure, partitioning, ATPG, DFT, RTL, isolation, balanced structure
25Irith Pomeranz, Sudhakar M. Reddy Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Thomas W. Williams, Rohit Kapur Design for Testability in Nanometer Technologies; Searching for Quality. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
25Juan A. Prieto, Adoración Rueda, Ian A. Grout, Eduardo J. Peralías, José L. Huertas, Andrew M. D. Richardson An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Irith Pomeranz, Sudhakar M. Reddy On Full Reset as a Design-For-Testability Technique. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
24Frank te Beest, Kees van Berkel, Ad M. G. Peeters Adding Synchronous and LSSD Modes to Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF design for testability, asynchronous circuits, scan test, LSSD
24José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
24Wang-Dauh Tseng, Kuochen Wang Testable Design and Testing of MCMs Based on Multifrequency Scan. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF boundary scan architecture, multifrequency test, smart substrate, technology mixed, design for testability, VHDL, multichip module
24Claudio Costi, Micaela Serra, Donatella Sciuto A new DFT methodology for sequential circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF design for testability, ATPG, fault coverage, scan design, test application time
24Bruce F. Cockburn Tutorial on semiconductor memory testing. Search on Bibsonomy J. Electronic Testing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF Design for testability, fault models, functional test, memory testing, memory design
24Irith Pomeranz, Sudhakar M. Reddy Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Loganathan Lingappan, Niraj K. Jha Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Loganathan Lingappan, Niraj K. Jha Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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