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Searching for phrase digital arithmetic (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1975-1989 (22) 1990 (19) 1991-1992 (27) 1993 (18) 1994-1995 (37) 1996-2000 (16) 2002-2018 (11)
Publication types (Num. hits)
article(106) incollection(1) inproceedings(43)
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Found 150 publication records. Showing 150 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
48Chin-Long Wey, Haiyan Wang, Cheng-Ping Wang A self-timed redundant-binary number to binary number converter for digital arithmetic processors. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF convertors, self-timed redundant-binary number to binary number converter, digital arithmetic processors, self-timed converter circuit, variable conversion time, statistical upper bound, delays, digital arithmetic, propagation delay, redundant number systems
36John L. Gustafson, Quinn Snell HINT: A new way to measure computer performance. Search on Bibsonomy HICSS (2) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF computer performance measurement, computer speeds, hierarchical integration, QUIPS work measure, quality improvements per second, memory regimes, memory size, hand calculation, sequential programming environments, performance evaluation, algorithms, scalability, computer architecture, computer architectures, digital arithmetic, digital arithmetic, portability, supercomputers, execution times, precision, memory bandwidth, computational performance, HINT, parallel programming environments, storage capacity
35Saeid Sadeghi-Emamchaie, Graham A. Jullien, Vassil S. Dimitrov, William C. Miller Digital Arithmetic Using Analog Arrays. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Cellular Neural Networks, Double-Base Number System, Analog VLSI
32Colin D. Walter Faster Modular Multiplication by Operand Scaling. Search on Bibsonomy CRYPTO The full citation details ... 1991 DBLP  DOI  BibTeX  RDF Fast Computer Arithmetic, Digital Arithmetic Methods, RSA Algorithm, Cryptography, Modular Multiplication
28Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera Radix-4 Vectoring Cordic Algorithm And Architectures. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF radix-4 vectoring CORDIC algorithm, radix-4 vectoring CORDIC architectures, vectoring mode, microrotations, zero skipping technique, recursive architectures, matrix triangularization, rotation angle, computational complexity, complexity, parallel architectures, singular value decomposition, SVD, signal processing, digital arithmetic, digital arithmetic, matrix algebra, pipelined architectures
25Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien Digital Multiplication using Continuous Valued Digits. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
15Andreas Persson, Lars Bengtsson Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems. Search on Bibsonomy Signal Processing Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Signed-digit, Moduli-selection, Residue number system, FIR filters, Converters
14Valeria Garofalo, Nicola Petra, Ettore Napoli Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2011 DBLP  DOI  BibTeX  RDF truncated multipliers, maximum error, digital arithmetic, error analysis, Multiplication, error compensation
14José A. Tierno, Sergey V. Rylov, Alexander Rylyakov, Montek Singh, Steven M. Nowick An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. Search on Bibsonomy ASYNC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF PRML read channel, magnetic recording, asynchronous pipeline, digital arithmetic, FIR filter, dynamic logic, high-throughput, low-latency, distributed arithmetic, mixed timing
14John N. Coleman, E. I. Chester, Christopher I. Softley, Jiri Kadlec Arithmetic on the European Logarithmic Microprocessor. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF interpolation, Digital arithmetic, logarithmic number system
14R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili A Low Power Floating Point Accumulator. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF low power CMOS, Digital arithmetic, VLSI architecture, floating point
14Vassil S. Dimitrov, Graham A. Jullien, William C. Miller Algorithms for Multi-Exponentiation Based on Complex Arithmetic. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1997 DBLP  DOI  BibTeX  RDF multi-exponentiation algorithms, binary-like complex arithmetic, multiple modular exponentiation operations, performance, cryptographic protocols, digital arithmetic
14Julio Villalba, Tomás Lang Low latency word serial CORDIC. Search on Bibsonomy ASAP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF word serial CORDIC, vectoring operation modes, digital arithmetic, iterations, scaling factor
14Jaswinder Pal Singh, A. Kumar, Sanjeev Kumar A multiplier generator for Xilinx FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
14R. D. (Shawn) Blanton, John P. Hayes Design of a fast, easily testable ALU. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit
14Albrecht P. Stroele Test response compaction using arithmetic functions. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF arithmetic functions, combinational faults, underflow, feed back, logic testing, built-in self test, digital arithmetic, test pattern generation, adders, circuits, registers, aliasing probability, overflow, subtracters, test response compaction, arithmetic logic units
14Ching-Long Su, Yin-Tsung Hwang Distributed arithmetic-based architectures for high speed IIR filter design. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF high speed IIR filter, pipelining techniques, SPDM technology, parallel processing, parallel architectures, digital arithmetic, recursion, recursive filters, Distributed Arithmetic, IIR filters, DSP applications
14Jean-Claude Bajard, Laurent-Stéphane Didier, Jean-Michel Muller A New Euclidean Division Algorithm For Residue Number Systems. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Euclidean division algorithm, large moduli, very large integers, high-radix division method, parallel computer, computational geometry, digital arithmetic, residue number systems, residue number systems, floating point arithmetic, floating-point arithmetic, modular arithmetic, special-purpose architecture
14Leilei Song, Keshab K. Parhi Efficient Finite Field Serial/Parallel Multiplication. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF finite field serial/parallel multiplication, finite field arithmetic architectures, bit-serial/parallel finite field multiplier, standard basis representation, optimal primitive polynomials, minimum hardware complexity, semi-systolic architecture, computational complexity, cryptography, cryptography, encoding, digital arithmetic, polynomials, multiplying circuits, VLSI implementation, coding theory
14Weng-Fai Wong, Eiichi Goto Fast Evaluation of the Elementary Functions in Single Precision. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1995 DBLP  DOI  BibTeX  RDF table-based algorithms, Digital arithmetic, error analysis, elementary functions
14S. M. Aziz A C-testable modified Booth's array multiplier. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier
14Luis A. Montalvo, Alain Guyot Svoboda-Tung division with no compensation. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Svoboda-Tung division, radix-b division algorithm, iteration overflow, most significant digits, radix-b algorithm, IEEE normalised divisor, pre-scaling technique, stepwise approximation, VLSI, iterative methods, digital arithmetic, VLSI implementation, prescalers, dividing circuits
14D. V. Poornaiah, P. V. Ananda Mohan Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron
14Priyadarsan Patra, Donald S. Fussell Fully asynchronous, robust, high-throughput arithmetic structures. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers
14Hakim Bederr, Michael Nicolaidis, Alain Guyot Analytic approach for error masking elimination in on-line multipliers. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF error masking elimination, online multipliers, high precision numbers, scan design approach, internal state observability, DFT approach, sequential circuits, digital arithmetic, fault coverage, multiplying circuits, area overhead
14Tomás Lang, Paolo Montuschi Very-high radix combined division and square root with prescaling and selection by rounding. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF very-high radix combined division and square root, digital arithmetic, rounding, prescaling
14Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata O(n)-depth circuit algorithm for modular exponentiation. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF O(n)-depth circuit algorithm, polynomial-size combinational circuit algorithm, n-bit modular exponentiation, n-bit binary integers, square-and-multiply method, public key cryptography, combinational circuits, digital arithmetic, modular exponentiation
14Milos D. Ercegovac, Tomás Lang Sign detection and comparison networks with a small number of transitions. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF comparison networks, signal transitions, iterative implementation, k-bit modules, digital arithmetic, flip-flops, tree network, sign detection
14Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin Reducing the number of counters needed for integer multiplication. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF counting circuits, reasonably small integers, partial product accumulation, aperiodic convolution, convolution algorithms, partial product formulation, fairly large integers, digital arithmetic, multiplying circuits, counters, integer multiplication
14Belle W. Y. Wei, He Du, Honglu Chen A complex-number multiplier using radix-4 digits. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF complex-number multiplier, radix-4 digits, arithmetic datapath, complex-number digital signal processor, binary signed digits, fast multiplication, compact layout, three-multiplication scheme, radix-4 operands, delays, delay, encoding, digital arithmetic, multiplying circuits, binary additions, coding scheme
14Vijay K. Jain, L. Lin High-speed double precision computation of nonlinear functions. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-speed double precision computation, interpolative approach, third degree polynomial, image processing, interpolation, interpolation, scientific computing, digital arithmetic, multiplications, coprocessors, coprocessors, real-time image processing, nonlinear functions, silicon area
14Seokjin Kim, Ramalingam Sridhar A local clocking approach for self-timed datapath designs. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits
14Hans Lindkvist, Per Andersson Dynamic CMOS circuit techniques for delay and power reduction in parallel adders . Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF dynamic CMOS circuit techniques, delay reduction, parallel adders, high-speed adders, Manchester-carry chains, clock/data precharged dynamic logic blocks, carry calculation trees, parallel processing, VLSI, delays, logic design, digital arithmetic, power consumption, adders, CMOS logic circuits, power reduction, carry logic
14Edmund M. Clarke, Masahiro Fujita, Xudong Zhao Hybrid decision diagrams. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF MTBDDs, arithmetic circuits verification, boolean vectors, hybrid decision diagrams, linear expressions, multi-terminal binary decision diagrams, symbolic model checking algorithms, computational complexity, time complexity, digital arithmetic, binary decision diagrams, circuit analysis computing, integers, BMDs
14Noam Nisan, Avi Wigderson Lower Bounds for Arithmetic Circuits via Partial Serivatives (Preliminary Version). Search on Bibsonomy FOCS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF restricted classes, computational complexity, lower bounds, digital arithmetic, polynomials, logic circuits, arithmetic circuits, multivariate polynomials, complexity measure, minimisation of switching nets, partial derivatives
14Mallika De, Bhabani P. Sinha Testing of a parallel ternary multiplier using I/sup 2/L logic. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
14Tzu-Hsi Pan, Hyon-Sok Kay, Youngsun Chun, Chin-Long Wey High-radix SRT division with speculation of quotient digits . Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-radix SRT division, quotient digits, quotient-digit selection table, speculated quotient digit, quotient-digit correction, digital arithmetic, table lookup, look-up table
14Michael J. Schulte, Earl E. Swartzlander Jr. A coprocessor for accurate and reliable numerical computations. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF reliable numerical computations, direct hardware support, logic design, digital arithmetic, interval arithmetic, hardware design, coprocessors, coprocessor, numerical computations
14Menghui Zheng, Alexander Albicki Low power and high speed multiplication design through mixed number representations. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products
14Tudor Jebelean Design of a systolic coprocessor for rational addition. Search on Bibsonomy ASAP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF systolic coprocessor, rational addition, exact division, field programmable gate arrays, parallel architectures, systolic arrays, digital arithmetic, multiplication, addition, subtraction, rational numbers, GCD
14Michael J. Schulte, Earl E. Swartzlander Jr. Hardware Designs for Exactly Rounded Elemantary Functions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF Chebyshev approximation, summing circuits, exactly rounded elementary functions, multi-operand adder, Chebyshev series approximation, single-precision floating point numbers, chip area, 1.0-micron CMOS technology, computational delay, exact rounding, argument reduction, computer arithmetic, digital arithmetic, polynomials, CMOS integrated circuits, multiplying circuits, square-root, hardware designs, reciprocal, approximation theory, polynomial approximation, special-purpose hardware, parallel multiplier, 1 micron
14Milos D. Ercegovac, Tomás Lang, Paolo Montuschi Very-High Radix Division with Prescaling and Selection by Rounding. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF very-high radix division, quotient-digit selection, carry-save, computer arithmetic, digital arithmetic, selection, rounding, redundant representation, prescaling, carry logic, division algorithm
14Weng-Fai Wong, Eiichi Goto Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF hardware-based algorithms, elementary function computations, rectangular multipliers, common elementary functions, reciprocal square root, arc tangent, microscopic parallelism, floating point multiplication, scientific computations, digital arithmetic, error analysis, sine, cosine
14James Phillips, Stamatis Vassiliadis High-Performance 3-1 Interlock Collapsing ALU's. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF 3-1 interlock collapsing ALU, execution interlocks, multiple instruction issuing machines, parallel architectures, delay, digital arithmetic, CMOS technology, critical path, reduced instruction set computing, Boolean equations
14Jean-Michel Muller Some Characterizations of Functions Computable in On-Line Arithmetic. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF piecewise affine functions, operands, arbitrarily long length, computability, digital arithmetic, finite automata, multiplication, division, elementary functions, finite automaton, online computing, rational numbers
14Jean Vuillemin On Circuits and Numbers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF PROM, 2-adic integers, synchronous decision diagrams, BDD constructs, bit-serial circuits, reset signals, 2Z, arithmetic synthesis f, periodic binary constants, deeply binding synchronous enable, combinational circuit semantics, arbitrary precision, programmable active memories, specification languages, sequential circuits, combinational circuits, digital arithmetic, logic CAD, adders, digital circuits, arithmetic, combinatorial circuits, synchronous circuits, continuous functions, rational numbers
14Nariankadu D. Hemkumar, Joseph R. Cavallaro Redundant and On-Line CORDIC for Unitary Transformations. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF unitary transformations, two-sided unitary transformation, Jacobi-like methods, complex matrices, special-purpose processor array architectures, nonredundant CORDIC, online CORDIC, redundant CORDIC, Coordinate Rotation Digital Computer, parallel algorithms, parallel algorithms, computational complexity, parallel architectures, singular value decompositions, digital arithmetic, matrix algebra, eigenvalue, CORDIC, special purpose computers, eigenvalues and eigenfunctions, matrices
14James Demmel, Xiaoye S. Li Faster Numerical Algorithms via Exception Handling. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF fast numerical algorithms, unstable algorithms, LAPACK library, IEEE floating point arithmetic, parallel algorithms, parallel machines, exception handling, exception handling, digital arithmetic, linear algebra, convergence of numerical methods, eigenvalues and eigenfunctions, numerical linear algebra
14Peter Kornerup Digit-Set Conversions: Generalizations and Application. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF conditional sum addition, digit set conversion, multiplier recoding, nonredundant representation, on-the-fly conversion, parallel prefix computation, carry-lookahead techniques, computer arithmetic, digital arithmetic, multiplying circuits, redundant representation
14Dan Zuras More On Squaring and Multiplying Large Integers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF large integers, FFT multipliers, digital arithmetic, multiplying, multiplying circuits, squaring, data handling
14David M. Lewis Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF read-only storage, interleaved memory function interpolators, accurate LNS arithmetic unit, accuracy requirements, round to nearest, 91 kbit, interpolation, digital arithmetic, polynomials, error analysis, floating point, approximation theory, ROM, polynomial interpolation, 32 bit, storage requirements
14Peter Kornerup A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF systolic linear-array multiplier, right-shift algorithms, multiplier cell, digit-product terms, least significant digit first, active elements, module-multiplier, Montgomery module-reduction, RSA encryption, modular division, cryptography, logic design, systolic arrays, systolic array, digital arithmetic, multiplying circuits, latches, modular inverses, Hensel codes, digit-serial multiplier
14Stanislaw J. Piestrak Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF residue generators, multioperand modular adders, arithmetic error detecting codes, binary-to-residue number system, residue generator, digital arithmetic, adders, Chinese remainder theorem, residue number system, arithmetic codes, residue arithmetic, carry-save adders
14Helmut Hahn, Dirk Timmermann, Bedrich J. Hosticka, Bernold Rix A Unified and Division-Free CORDIC Argument Reduction Method with Unlimited Convergence Domain Including Inverse Hyperbolic Functions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF CORDIC argument reduction method, convergence domain, inverse hyperbolic functions, unified division-free argument reduction method, floating point implementation, fixed point implementation, digital arithmetic, mathematics computing
14M. Anwarul Hasan, Muzhong Wang, Vijay K. Bhargava A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Massey-Omura parallel multiplier, cyclically shifted versions, input cyclic shift, lower circuit complexity, redundancy, finite fields, digital arithmetic, polynomials, polynomials, multiplying circuits
14Hannes Brunner, Andreas Curiger, Max Hofstetter On Computing Multiplicative Inverses in GF(2^m). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF computing multiplicative inverses, modular standard basis inversion, Euclid's algorithm, area requirement, AT-complexity, digital arithmetic, polynomials, computation time, Galois fields, greatest common divisor, asymptotic complexity
14Giovanni Dimauro, Sebastiano Impedovo, Giuseppe Pirlo A New Technique for Fast Number Comparison in the Residue Number System. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF number comparison, theoretical validity, diagonal function, modulus, digital arithmetic, residue number system
14Kishore Kota, Joseph R. Cavallaro Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF numerical accuracy, hardware tradeoffs, CORDIC arithmetic, special-purpose processors, coordinate rotation digital computer, real-time signal processing, Y-reduction mode, inverse tangent function, floating-point CORDIC, special-purpose arrays, signal processing, digital arithmetic, hybrid architecture, implementation complexity
14Behrooz Parhami On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF zero detection, arithmetic support functions, generalized signed-digit number systems, OSD number representation, borrow-free subtraction, overflow handling, digital arithmetic, redundant number representations, carry-free addition, sign detection
14Elio D. Di Claudio, Gianni Orlandi, Francesco Piazza A Systolic Redundant Residue Arithmetic Error Correction Circuit. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF systolic redundant residue arithmetic error correction circuit, concurrent fault tolerance capability, redundant residue number system, high speed VLSI circuit realization, parallel systolic architecture, parallel algorithms, VLSI, systolic arrays, digital arithmetic, error correction, real-time applications, error recovery, decision table, processing element, transient errors, residue arithmetic, memory element
14Stamatis Vassiliadis, James Phillips, Bart Blaner Interlock Collapsing ALU's. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement
14Yu Hen Hu, S. Naganathan An Angle Recoding Method for CORDIC Algorithm Implementation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF angle recording method, CORDIC algorithm implementation, coordinate rotation digital computer, iterative arithmetic algorithm, generalized vector rotations, elementary rotation angles, signal processing, digital arithmetic, greedy algorithm
14Marcel Lapointe, Huu Tue Huynh, Paul Fortier Systematic Design of Pipelined Recursive Filters. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF systematic design, pipelined recursive filters, multiplication algorithm, most significant digit first, pipelining delays, minimum hardware, minimum latency, number system radix, second-order all-pole filter, radix-4 representation, delays, digital arithmetic, pipeline processing, multiplier, digital filters
14Jean Duprat, Jean-Michel Muller The CORDIC Algorithm: New Results for Fast VLSI Implementation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF sign functions, fast VLSI implementation, signed-digit implementation, carry-save representation, branching CORDIC method, constant normalization factor, online delay, cosine functions, VLSI, signal processing, digital arithmetic, CORDIC algorithm
14Hari Krishna, Jenn-Dong Sun On Theory and Fast Algorithms for Error Correction in Residue Number System Product Codes. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF residue number system product codes, single errors, double errors, multiple errors, additive overflow, computational complexity, computational complexity, error correction codes, encoding, digital arithmetic, error correction, error control, coding theory, computationally efficient algorithms
14Stephen E. Eldridge, Colin D. Walter Hardware Implementation of Montgomery's Modular Multiplication Algorithm. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Montgomery's modular multiplication, fast modular multiplication, digital arithmetic, hardware implementation, multiplying circuits
14Steven Arno, Ferrell S. Wheeler Signed Digit Representations of Minimal Hamming Weight. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF minimal Hamming weight, combinatorial techniques, uniform probability space, k-digit integers, online algorithm, digital arithmetic, probability distributions, random variable, Markov chain analysis, signed digit representations
14Raymond E. Fowkes Hardware Efficient Algorithms for Trigonometric Functions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF hardware efficient algorithms, inverse functions, common TTL MSI logic, digital arithmetic, square root, sine, cosine, trigonometric functions
14Eric M. Schwarz, Michael J. Flynn Parallel High-Radix Nonrestoring Division. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF parallel high-radix nonrestoring division, quotient estimation, generalized partial remainder, carry propagate adder, high-radix division, logic design, logic design, latency, computer arithmetic, digital arithmetic, combinatorial algorithm, SRT division
14Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao Berger Check Prediction for Array Multipliers and Array Dividers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Berger check prediction, array dividers, closed-form check-predicting equations, digital arithmetic, multiplying circuits, array multipliers, dividing circuits
14Jean Duprat, Yvan Herreros, Sylvanus Kla New Redundant Representations of Complex Numbers and Vectors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF n-dimensional vectors, digital arithmetic, multiplication, redundant representation, complex numbers, carry-free addition, signed-digit number systems, polygonal representation
14Benjamin Arazi Architectures for Exponentiation Over GF(2^n) Adopted for Smartcard Application. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF exponentiation circuits, smartcard-based circuitry, structure regularity, dynamic shift registers, cryptography, smart cards, digital arithmetic, public key, time-space tradeoff, linear operation
14Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders
14Benjamin Arazi A Circular Binary Search. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF circular binary search, ordered linear array, circular array, digital arithmetic, codes, search problems, modular arithmetic, parity, Hamming weight, binary representation
14Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Mark D. Winkel Applying Features of IEEE 754 to Sign/Logarithm Arithmetic. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF sign/logarithm arithmetic, standard floating point arithmetic, multilayer sign/logarithm format, denormalized values, NaNs, logarithmic denormalized arithmetic algorithms, standards, digital arithmetic, number theory, zeros, 32 bit, infinities, IEEE 754
14Peter R. Cappello, Willard L. Miranker Systolic Super Summation with Reduced Hardware. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF systolic super summation, reduced hardware, cellular apparatus, sieve-like cellular array, fixed-point numbers, pipelined array, architectural regularity, VLSI circuit technology, systolic arrays, digital arithmetic, floating-point numbers
14Barry S. Fagin Fast Addition of Large Integers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF computation time asymmetry, large integers, massively parallel algorithms, average case behavior, large n-bit additions, multiple bits, parallel algorithms, computational model, digital arithmetic, massively parallel processor, binary addition, carry-lookahead
14Tomás Lang, Paolo Montuschi Higher Radix Square Root with Prescaling. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF higher radix square root, radicand, result-digit selection, double-precision square root, complexity, pipelining, online algorithms, digital arithmetic, multiplication, division, multiplying circuits, number theory, prescaling, dividing circuits
14Mi Lu, Jen-Shiun Chiang A Novel Division Algorithm for the Residue Number System. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF sign magnitude arithmetic division, signed number division, overflow detection, digital arithmetic, search problems, residue number system, number theory, binary search, algorithm theory, dividing circuits, parity checking, sign detection, division algorithm
14Jeong-A Lee, Tomás Lang Constant-Factor Redundant CORDIC for Angle Calculation and Rotation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF rotation direction, angle calculation, constant-factor redundant-CORDIC, plane rotations, correcting iterations, radix-4, convergence, iterative methods, digital arithmetic, number theory, convergence of numerical methods, algorithm theory, scale factor, radix-2
14Milos D. Ercegovac, Tomás Lang On-the-Fly Rounding. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF digit rounding, digit-serial form, most significant digit, least significant, redundant addition, result-digit, signed-digit set, computing arithmetic, digital arithmetic, number theory, digit-recurrence algorithms, online arithmetic
14Jordi Cortadella, José M. Llabería Evaluation of A + B = K Conditions Without Carry Propagation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF parallel adders, carry propagation delay, performance, digital arithmetic, response time, adders
14Isaac D. Scherson, David A. Kramer, Brian D. Alleyne Bit-Parallel Arithmetic in a Massively-Parallel Associative Processor. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF bit-parallel arithmetic, massively-parallel associative processor, storage cells, floating point data, VLSI, VLSI, parallel architectures, fast Fourier transform, fast Fourier transforms, digital arithmetic, matrix multiplication, multiplication, division
14Alexander Skavantzos, Poornachandra B. Rao New Multipliers Modulo 2^N - 1. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF modulo 2/sup N/-1, ROM bits, digital arithmetic, multiplication, multipliers, multiplying circuits, additions, squaring, look-up tables, cyclic convolution
14Chein-Wei Jen, Ding-Ming Kwai Data Flow Representation of Iterative Algorithms for Systolic Arrays. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF data flow representation, algebraic representation, modeling, parallel architectures, systolic arrays, systolic arrays, digital arithmetic, generating function, iterative algorithms, dependence graph, power series, geometric representation
14Dirk Timmermann, Helmut Hahn, Bedrich J. Hosticka Low Latency Time CORDIC Algorithms. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF constant scale factor, redundant addition, latency time, computational complexity, parallel architecture, iterative methods, digital arithmetic, adders, number theory, CORDIC algorithms
14Ronald J. Cosentino, John J. Vaccaro Adaptation of the Mactaggart and Jack Complex Multiplication Algorithm for Floating-Point Operators. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF Mactaggart complex multiplication, Jack complex multiplication algorithm, floating-point operators, vector cross-products, digital arithmetic, matrix multiplication, hardware implementation
14Zhi-Jian (Alex) Mou, Francis Jutand "Overturned-Stairs" Adder Trees and Multiplier Design. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF VLSI circuit layout, multioperand adders, Overturned-Stairs trees, 2's complement parallel multiplier, VLSI, logic design, digital arithmetic, trees (mathematics), adders, multiplying circuits, Wallace trees
14Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang ELM-A Fast Addition Algorithm Discovered by a Program. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF simple processors tree, addition algorithm, ELM, augend, addend, VLSI CAD tool, CMOS VLSI circuits, computational complexity, digital arithmetic, FACTOR
14Naofumi Takagi A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF division subtraction, radix-4 modular multiplication hardware algorithm, residue calculation, repeated multiply-add, serial-parallel modular multiplier, cellular array structure, VLSI, cryptography, digital arithmetic, public-key cryptosystems, modular exponentiation, RSA cryptosystem, redundant representation, bit slice
14Xiaobo Hu, Ronald G. Harber, Steven C. Bass Expanding the Range of Convergence of the CORDIC Algorithm. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF coordinate rotational digital computer, range of convergence, numerical values, functional arguments, fixed-point hardware implementation, iterative methods, digital arithmetic, roundoff errors, CORDIC algorithm
14Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa Pseudorandom Rounding for Truncated Multipliers. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF truncated multipliers, pseudorandom rounding, digital arithmetic, multiplications, rounding, floating-point numbers, multiple-precision
14Henk J. Sips, Hai-Xiang Lin An Improved Vector-Reduction Method. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF symmetric reduction methods, pipelined vector-reduction method, asymmetric reduction methods, digital arithmetic, pipeline processing
14Demetrios K. Kostopoulos An Algorithm for the Computation of Binary Logarithms. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF binary logarithms computation, base-2 logarithm, binary number, base-N, algorithm, digital arithmetic, iterations, algorithm theory, microcode
14Stamatis Vassiliadis, Eric M. Schwarz, Baik Moon Sung Hard-Wired Multipliers with Encoded Partial Products. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF hardwired multipliers, encoded partial products, multibit overlapped scanning multiplication algorithm, sign-magnitude, encoding, digital arithmetic, multiplying circuits, two's complement
14Fang-shi Lai, Ching-Farn Eric Wu A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF hybrid number system processor, floating-point number system, geometric, digital arithmetic, multiplication, division, square root, logarithmic number system, square, complex arithmetic
14Giuseppe Alia, Enrico Martinelli A VLSI Modulo m Multiplier. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF modulo m multiplier, residue multiplier, computational complexity, VLSI, VLSI, digital arithmetic, modular multiplications
14Chaitali Chakrabarti, Joseph JáJá VLSI Architectures for Multidimensional Transforms. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF multidimensional transforms, linear separable transforms, fixed-precision arithmetic, computational complexity, transforms, computer architecture, digital arithmetic, VLSI architectures
14Sung Je Hong The Design of a Testable Parallel Multiplier. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF testable parallel multiplier, summand-counter, test generation, digital arithmetic, multiplying circuits
14Belle W. Y. Wei, Clark D. Thompson Area-Time Optimal Adder Design. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF area-time optimal adder design, VLSI parallel adder, component cells, static CMOS, floating-point processor, 66 bit, VLSI, dynamic programming, dynamic programming, logic design, digital arithmetic, adders, CMOS integrated circuits, modular design
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