The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for phrase fault coverage (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1972-1985 (15) 1986-1987 (15) 1988 (21) 1989-1990 (34) 1991 (19) 1992 (27) 1993 (24) 1994 (37) 1995 (69) 1996 (78) 1997 (67) 1998 (70) 1999 (95) 2000 (95) 2001 (68) 2002 (99) 2003 (104) 2004 (93) 2005 (90) 2006 (78) 2007 (69) 2008 (75) 2009 (30) 2010 (18) 2011-2012 (19) 2013-2015 (15) 2016-2017 (16) 2018 (4)
Publication types (Num. hits)
article(497) inproceedings(946) phdthesis(1)
Venues (Conferences, Journals, ...)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 2136 occurrences of 698 keywords

Results
Found 1444 publication records. Showing 1444 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
89Ameet Bagwe, Rubin A. Parekhji Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
86Hailong Cui, Sharad C. Seth, Shashank K. Mehta Modeling Fault Coverage of Random Test Patterns. Search on Bibsonomy J. Electronic Testing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF fault-coverage prediction, cost-benefit analysis of fault simulation, variance of fault coverage, BIST, probabilistic model
82Albert F. Myers k-out-of-n: G System Reliability With Imperfect Fault Coverage. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
72Gabriel M. Silberman, Ilan Y. Spillinger Using functional fault simulation and the difference fault model to estimate implementation fault coverage. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
70Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas Statistical path delay fault coverage estimation for synchronous sequential circuits. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
69Peter C. Maxwell, Robert C. Aitken IDDQ testing as a component of a test suite: The need for several fault coverage metrics. Search on Bibsonomy J. Electronic Testing The full citation details ... 1992 DBLP  DOI  BibTeX  RDF quality, fault coverage, scan, functional testing, Current testing, physical defects
68Kwang-Ting Cheng Transition fault testing for sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
65Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment. Search on Bibsonomy DFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
65Albert F. Myers, Antoine Rauzy Efficient Reliability Assessment of Redundant Systems Subject to Imperfect Fault Coverage Using Binary Decision Diagrams. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
64Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell Statistical methods for delay fault coverage analysis. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities
64Irith Pomeranz, Sudhakar M. Reddy Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
64Wangqi Qiu, Xiang Lu, Jing Wang 0006, Zhuo Li 0001, D. M. H. Walker, Weiping Shi A Statistical Fault Coverage Metric for Realistic Path Delay Faults. Search on Bibsonomy VTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
64Yi Zhao, Sujit Dey Fault-coverage analysis techniques of crosstalk in chip interconnects. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
64Von-Kyoung Kim, Tom Chen, Mick Tegethoff Fault Coverage Estimation for Early Stage of VLSI Design. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
64Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu Defect Level Prediction Using Multi-Model Fault Coverage. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
59Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma Layout-aware scan chain synthesis for improved path delay fault coverage. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
59Von-Kyoung Kim, Tom Chen On comparing functional fault coverage and defect coverage for memory testing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
56Abdeslam En-Nouaary, Ferhat Khendek, Rachida Dssouli Fault Coverage in Testing Real-Time Systems. Search on Bibsonomy RTCSA The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Real-Time Systems, Testing, Specification, Implementation, Timed Automata, Fault Coverage
56Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. Search on Bibsonomy VTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
55Jayant Deodhar, Spyros Tragoudas Color Counting and its Application to Path Delay Fault Coverage. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
55Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul A test evaluation technique for VLSI circuits using register-transfer level fault modeling. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
55Irith Pomeranz, Sudhakar M. Reddy A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
54William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli Delay fault coverage, test set size, and performance trade-offs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
54Sumit Ghosh, Tapan J. Chakraborty On behavior fault modeling for digital designs. Search on Bibsonomy J. Electronic Testing The full citation details ... 1991 DBLP  DOI  BibTeX  RDF fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model
54Sezer Gören, F. Joel Ferguson Test sequence generation for controller verification and test with high coverage. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF finite state machine, Fault coverage, black box testing, X-machine
53Wilfried Daehn Fault simulation using small fault samples. Search on Bibsonomy J. Electronic Testing The full citation details ... 1991 DBLP  DOI  BibTeX  RDF confidence level, sampling, fault simulation, Bayesian estimation
53Albert F. Myers Achievable Limits on the Reliability of k-out-of-n: G Systems Subject to Imperfect Fault Coverage. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
52Xia Cai, Michael R. Lyu The effect of code coverage on fault detection under different testing profiles. Search on Bibsonomy ACM SIGSOFT Software Engineering Notes The full citation details ... 2005 DBLP  DOI  BibTeX  RDF software testing, fault detection, code coverage
52Xia Cai, Michael R. Lyu The effect of code coverage on fault detection under different testing profiles. Search on Bibsonomy A-MOST The full citation details ... 2005 DBLP  DOI  BibTeX  RDF software testing, fault detection, code coverage
51D. L. Tao, Carlos R. P. Hartmann A Novel Concurrent Error Detection Scheme for FFT Networks. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF concurrent error detection scheme, FFT networks, algorithm-based fault tolerancetechniques, digital signalprocessing chips, fault tolerant computing, fast Fourier transforms, error detection, fault coverage, system performance, roundoff errors, round-off errors
51T. W. Williams, Stephen K. Sunter How Should Fault Coverage Be Defined? Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
51Luca Simoncini, Arthur D. Friedman Incomplete Fault Coverage In Modular Miltiprocessor Systems. Search on Bibsonomy ACM Annual Conference (1) The full citation details ... 1978 DBLP  DOI  BibTeX  RDF
51Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal Improving accuracy in path delay fault coverage estimation. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
50Yung-Ruei Chang, Suprasad V. Amari, Sy-Yen Kuo OBDD-Based Evaluation of Reliability and Importance Measures for Multistate Systems Subject to Imperfect Fault Coverage. Search on Bibsonomy IEEE Trans. Dependable Sec. Comput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multistate system, importance measure, Reliability, fault-coverage, OBDD
50Karim Arabi, Bozena Kaminska Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Oscillation-Test Method, Parametric Fault Coverage, Analog Testing, Mixed-Signal Circuits
50V. Prepin, R. David Fault coverage of a long random test sequence estimated from a short simulation. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF long random test sequence, short simulation, fault coverage estimation, two-parameter model, fault diagnosis
50Marc Riedel, Janusz Rajski Fault coverage analysis of RAM test algorithms. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF RAM test algorithms, flexible software analysis program, arbitrary test sequences, coverage statistics, functional cell-array faults, fault state transition conditions, representative fault classes, fault diagnosis, integrated circuit testing, fault coverage, random-access storage, integrated memory circuits, semiconductor memories, test algorithms
50Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
48Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults
48Deepinder P. Sidhu, Ting-Kau Leung Formal Methods for Protocol Testing: A Detailed Study. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF NBS Class 4 Transport Protocol, protocol-test-sequence generation techniques, real-world communication protocols, protocols, fault detection, fault coverage, fault coverage, conformance testing, Monte Carlo methods, Monte Carlo simulation, failure analysis, test sequences, protocol implementation, protocol testing
47Irith Pomeranz, Sudhakar M. Reddy Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
47Mukund Sivaraman, Andrzej J. Strojwas Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fabrication process, coverage, delay testing, delay fault, path sensitization
47Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges Statistical estimation of delay fault detectabilities and fault grading. Search on Bibsonomy J. Electronic Testing The full citation details ... 1996 DBLP  DOI  BibTeX  RDF transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
47Yuyun Liao, D. M. H. Walker Optimal voltage testing for physically-based faults. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
47K. Vijayananda Distributed fault detection in communication protocols using extended finite state machines. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF distributed fault detection, run-time fault detection, coding defects, memory problems, protocol faults, vocabulary faults, sequencing faults, parallel decomposition method, multiple observers, distributed fault detection mechanism, fault tolerant computing, finite state machines, transport protocols, encoding, communication protocols, fault coverage, extended finite state machines
47Krishnendu Chakrabarty, John P. Hayes On the quality of accumulator-based compaction of test responses. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
47Eun Sei Park, M. Ray Mercer, Thomas W. Williams The Total Delay Fault Model and Statistical Delay Fault Coverage. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF delay fault model, delay fault coverage, statistical delay fault coverage, defect level model, logic testing, delay testing, delay faults
46Xiao Sun 0002, Carmie Hull Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. Search on Bibsonomy DFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF functional property, stuck-at fault coverage, verification coverage, UIO, verification, validation, ATPG, FSM, signature analysis, test application time
46Sanghyeon Baeg Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Yinan N. Shen, Fabrizio Lombardi, Donatella Sciuto Evaluation and improvement of fault coverage for verification and validation of protocols. Search on Bibsonomy SPDP The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
44Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams On the decline of testing efficiency as fault coverage approaches 100%. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF single stuck-at fault model, ISCAS benchmark circuits, nontarget defects, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, manufacturing process, test quality, production testing, testing efficiency, circuit sizes
44Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu Fault modeling and testing of retention flip-flops in low power designs. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
44Alexandre Petrenko Fault Model-Driven Test Derivation from Finite State Models: Annotated Bibliography. Search on Bibsonomy MOVEP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
43Vadim Trenkaev, Myungchul Kim, Soonuk Seol Interoperability Testing Based on a Fault Model for a System of Communicating FSMs. Search on Bibsonomy TestCom The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
43Zhen Chen, Boxue Yin, Dong Xiang Conflict driven scan chain configuration for high transition fault coverage and low test power. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
43Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Chen Fu, Richard P. Martin, Kiran Nagaraja, Thu D. Nguyen, Barbara G. Ryder, David Wonnacott Compiler-Directed Program-Fault Coverage for Highly Available Java Internet Services. Search on Bibsonomy DSN The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
43Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
42Mitrajit Chatterjee, Dhiraj K. Pradhan A BIST Pattern Generator Design for Near-Perfect Fault Coverage. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF core logic, built-in self-test, synthesis, fault coverage, Linear feedback shift registers, test pattern generation, scan, SOC
42Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das Delay Fault Coverage Enhancement Using Variable Observation Times. Search on Bibsonomy J. Electronic Testing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF statistical delay fault coverage, delay test observation times, delay fault testing
42Mitrajit Chatterjee, Dhiraj K. Pradhan A novel pattern generator for near-perfect fault-coverage. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF near-perfect fault-coverage, onchip BIST, GLFSR, logic mapping technique, weighted pattern technique, logic testing, built-in self test, integrated circuit testing, design methodology, combinational circuits, automatic testing, integrated logic circuits, shift registers, combinational logic, digital integrated circuits, pattern generator, single stuck-at fault
42Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche Test Challenges in Nanometer Technologies. Search on Bibsonomy J. Electronic Testing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF circuit marginality testing, process marginality testing, defect based testing, path delay testing
41Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. Search on Bibsonomy J. Electronic Testing The full citation details ... 2003 DBLP  DOI  BibTeX  RDF static faults, fault models, fault coverage, memory tests, dynamic faults, fault primitives
41Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy Resource-Constrained Compaction of Sequential Circuit Test Sets. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
41Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara On Test Generation with A Limited Number of Tests. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
41Margot Karam, Gabriele Saucier Functional versus random test generation for sequential circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1993 DBLP  DOI  BibTeX  RDF simulation, Finite state machine, functional testing, graph traversal
41Michael S. Hsiao On Non-Statistical Techniques for Fast Fault Coverage Estimation. Search on Bibsonomy J. Electronic Testing The full citation details ... 1999 DBLP  DOI  BibTeX  RDF fault coverage estimation, hyperactivity reduction, test generation, fault simulation, tolerance
41André Postma, Gerie Hartman, Thijs Krol Removal of all Faulty Nodes from a Fault-Tolerant Service by means of Distributed Diagnosis with Imperfect Fault Coverage. Search on Bibsonomy EDCC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
41Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Jien-Chung Lo Analysis of a BICS-Only Concurrent Error Detection Method. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF unsafe probability, reliability, fault coverage, testability, concurrent error detection, built-in current sensors, operating speed
41Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal Compaction-based test generation using state and fault information. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
40Warren H. Debany Jr., Kevin A. Kwiat, Sami A. Al-Arian A Method for Consistent Fault Coverage Reporting. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Joseph L. A. Hughes Multiple fault detection using single fault test sets. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
39Wei Li 0023, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Shambhu J. Upadhyaya, Kewal K. Saluja A new approach to the design of built-in self-testing PLAs for high fault coverage. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
39A. J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik March LR: a test for realistic linked faults. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF disturb faults, March LR, March LRD, March LRDD, fault diagnosis, integrated circuit testing, fault models, fault coverage, march tests, integrated memory circuits, semiconductor memories, linked faults
39C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal A STAFAN-like functional testability measure for register-level circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
39Bjørg Reppen, Einar J. Aas Combined probabilistic testability calculation and compact test generation for PLAs. Search on Bibsonomy J. Electronic Testing The full citation details ... 1991 DBLP  DOI  BibTeX  RDF probabilistic testability, Fault coverage, test pattern generation, programmable logic arrays
39Irith Pomeranz, Sudhakar M. Reddy Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38V. R. Devanathan Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng An almost full-scan BIST solution-higher fault coverage and shorter test application time. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF SPITFIRE, scalable parallel algorithms, test set partitioned fault simulation, synchronous parallel algorithms, sequential VLSI circuits, VLSI, fault coverage
38N.-C. Lai, S.-J. Wang, Y.-H. Fu Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Amitava Majumdar, Sarma B. K. Vrudhula Techniques for estimating test length under random test. Search on Bibsonomy J. Electronic Testing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF urn models, test quality, Circuit testing, waiting time distribution
38Marie-Lise Flottes, Christian Landrault, A. Petitqueux Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
38Michel Renovell, P. Huc, Yves Bertrand Bridging fault coverage improvement by power supply control. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits
37Heidrun Engel Data flow transformations to detect results which are corrupted by hardware faults. Search on Bibsonomy HASE The full citation details ... 1996 DBLP  DOI  BibTeX  RDF data flow transformations, corrupt result detection, hardware fault coverage, modified instruction, diverse data representation, modified instruction sequences, assembler level, high language level, fault tolerant computing, software faults, design diversity, hardware fault detection
37Ajay Khoche, Erik Brunvand A partial scan methodology for testing self-timed circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits
37Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
37Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell Fault coverage estimation by test vector sampling. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
37Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. Search on Bibsonomy ASPLOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF redundant multithreading, simultaneous multithreading (SMT), slipstream processor, chip multiprocessor (CMP), branch prediction, transient faults, value prediction, time redundancy
36Irith Pomeranz, Sudhakar M. Reddy n-pass n-detection fault simulation and its applications. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
36Fadi Maamari, Janusz Rajski A method of fault simulation based on stem regions. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
35Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi Enhancing Delay Fault Coverage through Low Power Segmented Scan. Search on Bibsonomy European Test Symposium The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Irith Pomeranz, Sudhakar M. Reddy Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35Suprasad V. Amari, Hoang Pham, G. Dill Optimal design of k-out-of-n: G subsystems subjected to imperfect fault-coverage. Search on Bibsonomy IEEE Trans. Reliability The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
35Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das Delay Fault Coverage Enhancement Using Multiple Test Observation Times. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
35Nur A. Touba Obtaining High Fault Coverage with Circular BIST Via State Skipping. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Circular BIST, Circular Self-Test Path, Conflict Matrix, Column Covering, Built-In Self-Test (BIST), Linear Feedback Shift Register, Pseudo-Random Testing, Digital Testing
Displaying result #1 - #100 of 1444 (100 per page; Change: )
Pages: [1][2][3][4][5][6][7][8][9][10][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license