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Searching for phrase fault model (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1978-1986 (15) 1987-1990 (31) 1991-1992 (23) 1993-1994 (24) 1995 (30) 1996 (28) 1997 (33) 1998 (27) 1999 (38) 2000 (45) 2001 (37) 2002 (48) 2003 (52) 2004 (53) 2005 (63) 2006 (50) 2007 (54) 2008 (64) 2009 (36) 2010-2012 (27) 2013-2014 (23) 2015-2016 (20) 2017-2018 (15)
Publication types (Num. hits)
article(257) inproceedings(576) phdthesis(3)
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Found 836 publication records. Showing 836 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
65Irith Pomeranz, Sudhakar M. Reddy Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
64Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools. Search on Bibsonomy J. Electronic Testing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF cell fault model (CFM), fault simulation, test pattern generation, stuck-at fault model
56Kwang-Ting Cheng Transition fault testing for sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
53Irith Pomeranz, Sudhakar M. Reddy A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
50Gabriel M. Silberman, Ilan Y. Spillinger Using functional fault simulation and the difference fault model to estimate implementation fault coverage. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
49Hsien-Sheng Hsiao, Yeh-Hao Chin, Wei-Pang Yang Reaching Fault Diagnosis Agreement under a Hybrid Fault Model. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fault diagnosis agreement, mixed fault model, Byzantine agreement, fault-tolerant distributed system, hybrid fault model
49Naim Ben Hamida, Khaled Saab, David Marche, Bozena Kaminska A perturbation based fault modeling and simulation for mixed-signal circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF analog circuit fault simulation, perturbation fault model, fault abstraction, structural fault modeling, perturbation estimation, fault observation, hierarchical analog fault simulator, complexity, test generation, CMOS, mixed-signal circuits, mixed analogue-digital integrated circuits, functional fault modeling, physical defects
46Sumit Ghosh, Tapan J. Chakraborty On behavior fault modeling for digital designs. Search on Bibsonomy J. Electronic Testing The full citation details ... 1991 DBLP  DOI  BibTeX  RDF fault coverage correlation, fault model, fault simulation, stuck-at fault, behavior model
46Chauchin Su, Shenshung Chiang, Shyh-Jye Jou Impulse response fault model and fault extraction for functional level analog circuit diagnosis. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Testing, Diagnosis, Analog Circuit
45Alexandre Petrenko Fault Model-Driven Test Derivation from Finite State Models: Annotated Bibliography. Search on Bibsonomy MOVEP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
44Hisashi Kondo, Kwang-Ting Cheng Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Selective IDDQ, Pseudo Stuck-at Fault, Sequential ATPG, Vector compaction, Test, Fault model, IDDQ, Leakage Fault
44Irith Pomeranz, Sudhakar M. Reddy A delay fault model for at-speed fault simulation and test generation. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Dajin Wang A Rectilinear-Monotone Polygonal Fault Block Model for Fault-Tolerant Minimal Routing in Mesh. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF fault tolerance, interconnection network, mesh, fault model, Adaptive routing
40Xijiang Lin, Janusz Rajski Propagation delay fault: a new fault model to test delay faults. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Klaus Echtle, Irene Eusgeld A Genetic Algorithm for Fault-Tolerant System Design. Search on Bibsonomy LADC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF analysis of fault-tolerant behaviour, genetic algorithm, Fault tolerance, fault model, fitness function
38Irith Pomeranz, Sudhakar M. Reddy Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Hideyuki Jitsumoto, Toshio Endo, Satoshi Matsuoka ABARIS: An Adaptable Fault Detection/Recovery Component Framework for MPIs. Search on Bibsonomy IPDPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Jan Torben Weinkopf, Klaus Harbich, Erich Barke Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Yinan N. Shen, Xiao-Tao Chen, Susumu Horiguchi, Fabrizio Lombardi On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model. Search on Bibsonomy ICPP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF CMOS fault model, multiple fault diagnosis, interconnection networks, fault diagnosis, lower bound, multistage interconnection networks, multistage interconnection networks, CMOS technology, stuck-open faults
35Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
34Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier Modeling of Crosstalk Fault in Defective Interconnects. Search on Bibsonomy PATMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF defect-based-crosstalk fault model, signal integrity losses, aggres-sor-victim, ABCD-model, crosstalk-hazards
34Alaa Ibrahim, Hany H. Ammar, Sherif M. Yacoub A Fault Model for Fault Injection Analysis of Dynamic UML Dynamic Specifications. Search on Bibsonomy ISSRE The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Verification an Validation, UML and statecharts, Fault Model, Fault Injection
34Vadim Trenkaev, Myungchul Kim, Soonuk Seol Interoperability Testing Based on a Fault Model for a System of Communicating FSMs. Search on Bibsonomy TestCom The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33Mohammad H. Azadmanesh, Roger M. Kieckhafer Exploiting Omissive Faults in Synchronous Approximate Agreement. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Approximate agreement, convergent voting algorithms, hybrid faults, clock synchronization, fault-tolerant distributed systems
33Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su A methodology for fault model development for hierarchical linear systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF closed loop systems, hierarchical linear systems, transfer function model, open-loop, element faults, benchmark state-variable filter, AC fault model, state variable filter, fault diagnosis, fault model, fault simulation, modules, Monte Carlo methods, Monte Carlo simulation, transfer functions, computation time, operational amplifiers, operational amplifiers, closed loop, analogue circuits
33Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo Test Generation for Multiple-Threshold Gate-Delay Fault Model. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Anyuan Yang, Jianchao Wang Fault-Tolerant Rearrangeable Permutation Network. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF losing-contact fault, Fault tolerance, routing, cluster computing, fault model, permutation, switching networks, Clos networks, rearrangeable
32Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
31Ronald D. Blanton, John P. Hayes On the properties of the input pattern fault model. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF fault testing, testing digital circuits, ATPG, fault models, faults, defects
31Chitra Babu, Harshini Ramnath Krishnan Fault model and test-case generation for the composition of aspects. Search on Bibsonomy ACM SIGSOFT Software Engineering Notes The full citation details ... 2009 DBLP  DOI  BibTeX  RDF aspect oriented programming, fault model, aspect composition, join point
31Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
31Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche Test Challenges in Nanometer Technologies. Search on Bibsonomy J. Electronic Testing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF circuit marginality testing, process marginality testing, defect based testing, path delay testing
30Evan Martin, Tao Xie A fault model and mutation testing of access control policies. Search on Bibsonomy WWW The full citation details ... 2007 DBLP  DOI  BibTeX  RDF test generation, fault model, mutation testing, access control policies
30Shweta Chary, Michael L. Bushnell Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli Delay fault coverage, test set size, and performance trade-offs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
30William A. Rogers, Jacob A. Abraham High level hierarchical fault simulation techniques. Search on Bibsonomy ACM Conference on Computer Science The full citation details ... 1985 DBLP  DOI  BibTeX  RDF
30Jayant Deodhar, Spyros Tragoudas Color Counting and its Application to Path Delay Fault Coverage. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
30Christophe Clavier, Benedikt Gierlichs, Ingrid Verbauwhede Fault Analysis Study of IDEA. Search on Bibsonomy CT-RSA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Collision Fault Analysis, Ineffective Fault Analysis, Random Fault Model, IDEA, Differential Fault Analysis
30Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi Diagnosing Single Faults for Interconnects in SRAM Based FPGAs. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF FPGA, testing, fault diagnosis, fault model
29Hugo Cheung, Sandeep K. Gupta Accurate modeling and fault simulation of Byzantine resistive bridges. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Amir Moradi 0001, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh A Generalized Method of Differential Fault Attack Against AES Cryptosystem. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Cryptanalysis, Smart Card, AES, Side Channel Attacks, Fault Attacks
29Zhen Jiang, Jie Wu 0001 A Limited-Global Fault Information Model for Dynamic Routing in n-D Meshes. Search on Bibsonomy IPDPS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF defective interconnects, defect’s severity, fault model, crosstalk, bridging fault
29Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap Fault Models and Test Procedures for Flash Memory Disturbances. Search on Bibsonomy J. Electronic Testing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF program disturbance, fault model, flash memory, test algorithms
29Samrat Goswami, Anupam Chanda, D. Roy Choudhury Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Testing FSM, Single State Transition Fault Model, Sequential Machine
29Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal SIGMA: a simulator for segment delay faults. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fault model, fault simulator, delay fault testing
29Jon S. Bækken, Roger T. Alexander A Candidate Fault Model for AspectJ Pointcuts. Search on Bibsonomy ISSRE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal Segment delay faults: a new fault model. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF segment delay faults, delay defect, distributed defect, rising transitions, falling transitions, transition tests, nonrobust tests, VLSI, fault diagnosis, logic testing, delays, integrated circuit testing, fault model, automatic testing, circuit analysis computing, robust tests, integrated circuit modelling, production testing, spot defect, manufacturing defects
29Lech Józwiak On the use of term trees for effective and efficient test pattern generation. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF term trees, structural automatic test pattern generation, fault discovery, structural fault model, term tree based ATPG algorithm, nonredundant faults, minimal test set, circuit redundancy, logic design, fault model, data representation, automatic test software
28Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante A New Functional Fault Model for FPGA Application-Oriented Testing. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
28Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu Defect Level Prediction Using Multi-Model Fault Coverage. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
28Ankan K. Pramanick, Sudhakar M. Reddy On the fault coverage of gate delay fault detecting tests. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
28Irith Pomeranz, Sudhakar M. Reddy The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
27Wangqi Qiu, Xiang Lu, Jing Wang 0006, Zhuo Li 0001, D. M. H. Walker, Weiping Shi A Statistical Fault Coverage Metric for Realistic Path Delay Faults. Search on Bibsonomy VTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
27Yi Zhao, Sujit Dey Fault-coverage analysis techniques of crosstalk in chip interconnects. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
27Jie Wu 0001 A Fault-Tolerant Adaptive and Minimal Routing Approach in 3-D Meshes. Search on Bibsonomy ICPADS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF 3-D meshes, fault tolerance, deadlock, adaptive routing, livelock, minimal routing
26Hisashi Kondo, Kwang-Ting Cheng An Efficient Compact Test Generator for IDDQ Testing. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Selective IDDQ, Pattern Compaction, Pseudo Stuck-at Fault, Essential Fault, Test, ATPG, Fault Model, Testability, IDDQ, Leakage Fault
26Dong Xiang, Jia-Guang Sun, Jie Wu 0001, Krishnaiyan Thulasiraman Fault-Tolerant Routing in Meshes/Tori Using Planarly Constructed Fault Blocks. Search on Bibsonomy ICPP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF extended local safety, unsafe systems, mesh/torus, fault-tolerant routing, Computational power
26Thorsten Schnier, Xin Yao 0001 Using Negative Correlation to Evolve Fault-Tolerant Circuits. Search on Bibsonomy ICES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
26Shyue-Kung Lu, Chien-Hung Yeh Enhancing Delay Fault Testability for Iterative Logic Array. Search on Bibsonomy PRDC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
26Jie Wu 0001 A Fault-Tolerant Adaptive and Minimal Routing Approach in n-D Meshes. Search on Bibsonomy ICPP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
26F. Joel Ferguson, John Paul Shen A CMOS fault extractor for inductive fault analysis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
26Irith Pomeranz, Sudhakar M. Reddy Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
26Irith Pomeranz, Sudhakar M. Reddy Generation of broadside transition fault test sets that detect four-way bridging faults. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
26Zhen Jiang, Jie Wu 0001 A Limited-Global Information Model for Dynamic Fault-Tolerant Routing in Cube-Based Multicomputers. Search on Bibsonomy NCA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
26Irith Pomeranz, Sudhakar M. Reddy Functional test generation for delay faults in combinational circuits. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF function-robust tests, functional delay fault model, delay faults, path delay faults, robust tests
26Robert C. Aitken Diagnosis of leakage faults with IDDQ. Search on Bibsonomy J. Electronic Testing The full citation details ... 1992 DBLP  DOI  BibTeX  RDF leakage fault model, Fault diagnosis, I DDQ testing
25Zhanglei Wang, Krishnendu Chakrabarty Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Hin-Sing Siu, Yeh-Hao Chin, Wei-Pang Yang Byzantine Agreement in the Presence of Mixed Faults on Processors and Links. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF synchronization, Byzantine agreement, fault-tolerant distributed system, hybrid fault model, general network
25C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal A STAFAN-like functional testability measure for register-level circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
25Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. Search on Bibsonomy FPL The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi On a Logical Fault Model H1SGLF for Enhancing Defect Coverage. Search on Bibsonomy Asian Test Symposium The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Kwang-Ting Cheng, Jing-Yang Jou A functional fault model for sequential machines. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
24Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute Comprehensive bridging fault diagnosis based on the SLAT paradigm. Search on Bibsonomy DDECS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Marco Ottavi, Hamidreza Hashempour, Vamsi Vankamamidi, Faizal Karim, Konrad Walus, André Ivanov On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits. Search on Bibsonomy DFT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita Fault Diagnosis of Physical Defects Using Unknown Behavior Model. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Huawei Li, Xiaowei Li 0001 Selection of Crosstalk-Induced Faults in Enhanced Delay Test. Search on Bibsonomy J. Electronic Testing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF automatic test pattern generation (ATPG), crosstalk, delay test, critical paths
24T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24Jon S. Bækken, Roger T. Alexander Towards a fault model for AspectJ programs: step 1 -- pointcut faults. Search on Bibsonomy WTAOP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Emmanuelle Dottax, Christophe Giraud, Matthieu Rivain, Yannick Sierra On Second-Order Fault Analysis Resistance for CRT-RSA Implementations. Search on Bibsonomy WISTP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Second Order, CRT-RSA, Fault Attacks, Countermeasure
24Marek Chrobak, Mathilde Hurand, Jirí Sgall Fast Algorithms for Testing Fault-Tolerance of Sequenced Jobs with Deadlines. Search on Bibsonomy RTSS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Christophe Giraud DFA on AES. Search on Bibsonomy AES Conference The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Baosheng Wang, Josh Yang, André Ivanov Reducing Test Time of Embedded SRAMs. Search on Bibsonomy MTDT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Embedded SRAM test, Inductive Fault Analysis, Memory Redundancy, March Test, Test Time
23Anjali Joshi, Mats Per Erik Heimdahl Behavioral Fault Modeling for Model-based Safety Analysis. Search on Bibsonomy HASE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Donatien Grolaux, Kevin Glynn, Peter Van Roy A Fault Tolerant Abstraction for Transparent Distributed Programming. Search on Bibsonomy MOZ The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker 0001, Stefan Spinner, Xiaoqing Wen Diagnosis of Realistic Defects Based on the X-Fault Model. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Yunzhan Gong, Wanli Xu, Xiaowei Li 0001 An Expression's Single Fault Model and the Testing Methods. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
23Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams On the decline of testing efficiency as fault coverage approaches 100%. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF single stuck-at fault model, ISCAS benchmark circuits, nontarget defects, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, manufacturing process, test quality, production testing, testing efficiency, circuit sizes
23Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel On Double Transition Faults as a Delay Fault Model. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
23Marco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF behavioral fault model, functional TPG
23Patrick H. S. Brito, Rogério de Lemos, Cecília M. F. Rubira Development of Fault-Tolerant Software Systems Based on Architectural Abstractions. Search on Bibsonomy ECSA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Dirk Niggemeyer, Elizabeth M. Rudnick Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Johannes Blömer, Jean-Pierre Seifert Fault Based Cryptanalysis of the Advanced Encryption Standard (AES). Search on Bibsonomy Financial Cryptography The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Secure Banking, Smart Cards, AES, Fault Attacks, Implementation Issues
23Zhen Jiang, Jie Wu 0001 A Limited-Global Fault Information Model for Dynamic Routing in 2-D Meshes. Search on Bibsonomy IPDPS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF 2-D meshes, safety levels, fault tolerance, routing, Dynamic faults
23Raphael R. Some, Won S. Kim, Garen Khanoyan, Leslie Callum, Anil Agrawal, John J. Beahan Software-Implemented Fault Injection Methodology for Design and Validation of System Fault Tolerance. Search on Bibsonomy DSN The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
23Andreas Polze, Janek Schwarz, Miroslaw Malek Automatic Generation of Fault-Tolerant CORBA-Services. Search on Bibsonomy TOOLS (34) The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Fault-Tolerance, Aspect-Oriented Programming, CORBA, Replication
23Weiwei Mao, Michael D. Ciletti A Simplified Six-waveform Type Method for Delay Fault Testing. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
23Tadashi Dohi, Shunji Osaki, Kishor S. Trivedi An Infinite Server Queueing Approach for Describing Software Reliability Growth - Unified Modeling and Estimation Framework. Search on Bibsonomy APSEC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
23Michele Favalli, Marcello Dalpasso, Piero Olivo Modeling and simulation of broken connections in CMOS IC's. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
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