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Publication years (Num. hits)
1984-1990 (33) 1991 (19) 1992 (29) 1993 (45) 1994 (72) 1995 (69) 1996 (58) 1997 (53) 1998 (97) 1999 (56) 2000 (65) 2001 (40) 2002 (61) 2003 (62) 2004 (50) 2005 (62) 2006 (69) 2007 (69) 2008 (51) 2009 (60) 2010 (48) 2011 (48) 2012 (55) 2013 (76) 2014 (69) 2015 (81) 2016 (76) 2017 (88) 2018 (70) 2019 (15)
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article(478) incollection(3) inproceedings(1245) phdthesis(19) proceedings(1)
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DAC(127) IEEE Trans. on CAD of Integrat...(93) DATE(72) ICCAD(62) IEEE Trans. VLSI Syst.(59) VLSI Design(57) ASP-DAC(56) ACM Trans. Design Autom. Elect...(47) FPGA(43) FPL(43) ICCD(37) ISCAS(33) HLSS(31) FCCM(28) FPT(25) ISQED(23) More (+10 of total 282)
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Found 1746 publication records. Showing 1746 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
83Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Application specific High-Level Synthesis, High-Level Synthesis for telecommunication, ATM
81Vijay Raghunathan, Srivaths Ravi 0001, Ganesh Lakshminarayana High-Level Synthesis with Variable-Latency Components. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF variable latency units, data dependent computation, area-delay tradeoffs, High-level synthesis, performance optimization
63Nilanjan Mukherjee 0001, H. Kassab, Janusz Rajski, Jerzy Tyszer Arithmetic built-in self test for high-level synthesis. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
61Min Xu, Fadi J. Kurdahi Layout-Driven RTL Binding Techniques for High-Level Synthesis. Search on Bibsonomy ISSS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF layout-driven register-transfer-level, binding techniques, chip level implementation, high level synthesis, high-level synthesis, design process
61Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac High-Level Synthesis with SIMD Units. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF SIMD functional units, High-level synthesis, high performance design
60Sumit Gupta, Rajesh K. Gupta 0001, Nikil D. Dutt, Alexandru Nicolau Coordinated parallelizing compiler optimizations and high-level synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF dynamic CSE, parallelizing transformations, presynthesis, embedded systems, high-level synthesis, Code motions, common subexpression elimination
60Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu 0001, Xu Cheng 0001, Jason Cong Bit-level optimization for high-level synthesis and FPGA-based acceleration. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF bit-level optimization, fpga, high-level synthesis
59Xiaowei Li 0001, Toshimitsu Masuzawa, Hideo Fujiwara Strong self-testability for data paths high-level synthesis. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF self-testability, testability constraints, interconnection assignment, test resources reusability, high level synthesis, high-level synthesis, design for testability, register transfer level, data flow graphs, data paths, register assignment
59Preeti Ranjan Panda, Nikil D. Dutt 1995 high level synthesis design repository. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF 1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units
59Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
56Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem Coordinated transformations for high-level synthesis of high performance microprocessor blocks. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF high-level synthesis, microprocessor design
56Youn-Long Lin Recent developments in high-level synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF high level synthesis, design methodology, VLSI design, design automation
55Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja Incorporating testability considerations in high-level synthesis. Search on Bibsonomy J. Electronic Testing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability
54Junhyung Um, Taewhan Kim Resource Sharing Combined with Layout Effects in High-Level Synthesis. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF resource allocation, high-level synthesis, layout
52Oliver Bringmann 0001, Wolfgang Rosenstiel, Carsten Menn Controller Estimation for FPGA Target Architectures during High-Level Synthesis. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA, controller, high-level synthesis, area estimation
52Alex Orailoglu Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF microarchitectural synthesis, dynamically reconfigurable ASICs, fault-tolerance scheme, band reconfiguration, multiple permanent faults, associated high-level synthesis procedure, hardware rebinding, high-level synthesis, application specific integrated circuits, graceful degradation
52Ahmad Abualsamid, Raed Alqadi, Parameswaran Ramanathan Distributed synthesis of real-time computer systems. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF engineering workstations, distributed synthesis, design library, processor estimation, application constraints, suitable architecture identification, application task scheduling, runtime speedup, scheduling, real-time systems, computational complexity, parallelization, CAD, distributed processing, high level synthesis, high-level synthesis, software libraries, workstation network, real-time computer systems, resource estimation, component library
52Santonu Sarkar, Anupam Basu, Arun K. Majumdar Synchronization of communicating modules and processes in high level synthesis. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF communicating modules, object oriented design framework, nonblocking channel, real life image processing, synchronization, high level synthesis, high level synthesis, application specific integrated circuits, synchronisation, object-oriented methods, component reuse, ASIC designs, image processing equipment
52Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu A comprehensive estimation technique for high-level synthesis. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
52Balakrishnan Iyer, Ramesh Karri, Israel Koren Phantom redundancy: a high-level synthesis approach for manufacturability. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fabrication-time reconfigurability, functional unit failure, microarchitecture synthesis, phantom redundancy, genetic algorithm, high level synthesis, high-level synthesis, redundancy, logic design, reconfigurable architectures, manufacturability, microarchitecture, circuit CAD
52Oliver Bringmann 0001, Wolfgang Rosenstiel Cross-Level Hierarchical High-Level Synthesis. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Hierarchical Synthesis, Complex Components, High-Level Synthesis
51Ireneusz Karkowski Architectural synthesis with possibilistic programming. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF possibilistic programming, fuzzy mathematical programming, simultaneous scheduling, FOAS, computational complexity, computational complexity, fuzzy logic, high level synthesis, high-level synthesis, circuit CAD, mathematical programming, possibility theory
51Levent Aksoy, Diego Jaccottet, Eduardo Costa 0001 Design of low complexity digital FIR filters. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low-level synthesis, multiple constant multiplications, multiplierless filter design, high-level synthesis, array multipliers
51Reinaldo A. Bergamaschi Bridging the domains of high-level and logic synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
50Tsung-Hsi Chiang, Lan-Rong Dung System-level verification on high-level synthesis of dataflow graph. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Jörg Henkel, Rolf Ernst, Ulrich Holtmann, Thomas Benner Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
49Reinaldo A. Bergamaschi, Andreas Kuehlmann A system for production use of high-level synthesis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
49Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade Hand-in-hand verification of high-level synthesis. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FSMD model, formal verification, high-level synthesis, equivalence checking
49Mikael R. K. Patel A design representation for high level synthesis. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF Data Structures, High Level Synthesis, Design Automation, Design Representation
48Jay K. Adams, John Alan Miller, Donald E. Thomas Execution-time profiling for multiple-process behavioral synthesis. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
47Greg Stitt, Frank Vahid Binary synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Binary synthesis, synthesis from software binaries, FPGA, hardware/software codesign, hardware/software partitioning, configurable logic, warp processors
47Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey High-level Synthesis of Multi-process Behavioral Descriptions. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Alan Su 0002, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee Eliminating False Loops Caused by Sharing in Control Path. Search on Bibsonomy ISSS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF false loops, control path sharing, timing validation, design sign-off phase, data path sharing, control logic sharing, removal algorithm, computation complexity, high level synthesis, high level synthesis, filter, resource sharing, logic minimization
46Anand Raghunathan, Niraj K. Jha SCALP: an iterative-improvement-based low-power data path synthesis system. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
46Zhenyu (Peter) Gu, Jia Wang 0003, Robert P. Dick, Hai Zhou Unified Incremental Physical-Level and High-Level Synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Fei Su, Krishnendu Chakrabarty High-level synthesis of digital microfluidic biochips. Search on Bibsonomy JETC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF scheduling, system-on-chip, High-level synthesis, microfluidics, biochips
46J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir A Heuristic for Clock Selection in High-Level Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF clock selection, heuristics, high-level synthesis, design space exploration, graph structure
46Andrew Stone, Elias S. Manolakos Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. Search on Bibsonomy ASAP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity
46Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong 0001, Anand Raghunathan, Niraj K. Jha A comprehensive high-level synthesis system for control-flow intensive behaviors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF control-flow intensive behaviors, high-level synthesis, low power design
46Salil Raje, Reinaldo A. Bergamaschi Generalized resource sharing. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF clique-partitioning-based algorithms, generalized resource sharing, global clique partitioning based framework, interconnect cost estimation, merging cost estimation, sharing possibilities, high level synthesis, high-level synthesis, functional unit, functional units
46Hans-Georg Martin Retiming for Circuits with Enable Registers. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF enable registers, circuit retiming, combinational paths, D-Flipflops, retiming algorithm, sequential elements, high level synthesis, high level synthesis, digital circuits
46Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
46Enric Musoll, Jordi Cortadella Scheduling and resource binding for low power. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF data-path power budget, low-power data-paths, scheduling, low power, high level synthesis, high-level synthesis, power consumption, adders, multipliers, logic circuits, data flow graphs, trading off, network synthesis, functional units, resource binding, resource-binding
46Miodrag Potkonjak, Anantha Chandrakasan Synthesis and selection of DCT algorithms using behavioral synthesis-based algorithm space exploration. Search on Bibsonomy ICIP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF DCT algorithms, behavioral synthesis-based algorithm space exploration, high level synthesis tools, behavioral design space, IC implementation, image processing, image processing, high level synthesis, discrete cosine transforms, discrete cosine transform, application specific integrated circuits, circuit layout CAD, video processing, fast algorithms, video signal processing, digital signal processing chips, design space
45Alex Orailoglu Microarchitectural synthesis for rapid BIST testing. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
45Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh A scheduling algorithm for optimization and early planning in high-level synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Scheduling, high-level synthesis, data flow graph, bipartite matching
45Pradeep Prabhakaran, Prithviraj Banerjee Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF timing driven synthesis, High-level synthesis, floorplanning
45Giacomo Buonanno, M. Pugassi, Mariagiovanna Sami A high-level synthesis approach to design of fault-tolerant systems. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF hardware-software system, design, embedded system, fault tolerant computing, high-level synthesis, reconfiguration, scheduling algorithm, cost, processor, fault-tolerant system
45Peter Grün, Petru Eles, Krzysztof Kuchcinski, Zebo Peng Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Petri net-based design representation, internal design representation, hardware structures, conflict freeness, hierarchical Petri net structure, CAMAD, complexity, parallelization process, Petri nets, high-level synthesis, automatic parallelization, design environment, safeness
44Byoungro So, Pedro C. Diniz, Mary W. Hall Using estimates from behavioral synthesis tools in compiler-directed design space exploration. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF synthesis techniques for reconfigurable computing, field-programmable-gate-array, high-level synthesis, rapid prototyping, design space exploration
44Raul Camposano, L. F. Saunders, R. M. Tabet VHDL as Input for High-Level Synthesis. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
43Soumya Pandit, Chittaranjan A. Mandal, Amit Patra A formal approach for high level synthesis of linear analog systems. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF L2 sensitivity, analog high level synthesis, linear systems, architecture exploration, state space model
43Vyas Krishnan, Srinivas Katkoori A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Jae-Jin Lee, Gi-Yong Song High-Level Synthesis Using SPARK and Systolic Array. Search on Bibsonomy ARC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
42Insup Shin, Seungwhun Paik, Youngsoo Shin Register allocation for high-level synthesis using dual supply voltages. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low power, high-level synthesis, register allocation, dual supply voltage
42Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer Estimation of BIST Resources During High-Level Synthesis. Search on Bibsonomy J. Electronic Testing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF built-in self-test, high-level synthesis, estimation
42Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF multiplexer re-structuring, low power, high-level synthesis, resource sharing, control-flow, module selection
42José M. Mendías, Román Hermida Correct High-Level Synthesis: a Formal Perspective. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF automatic formal synthesis, formal verification, high-level synthesis, streams
42Hsueh-Chih Yang, Lan-Rong Dung On multiple-voltage high-level synthesis using algorithmic transformations. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF loop shrinking, multiple voltage scheduling, high-level synthesis, retiming, unfolding, low power circuit
41Vyas Krishnan, Srinivas Katkoori Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41D. L. Springer, Donald E. Thomas Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
41Ki-Il Kum, Wonyong Sung Combined word-length optimization and high-level synthesis ofdigital signal processing systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
41Min Xu, Fadi J. Kurdahi Layout-driven RTL binding techniques for high-level synthesis using accurate estimators. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF FPGAs, high-level synthesis, floorplan, binding
41Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey Resource budgeting for Multiprocess High-level synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Oliver Bringmann 0001, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Synthesis Methodology, Configurable VHDL Components, VHDL, Rapid Prototyping, SDL
41Jie Gong, Chih-Tung Chen, Kayhan Küçükçakar Architectural Rule Checking for High-level Synthesis. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Rule Checking, Verification, High-level Synthesis
41Wayne H. Wolf Redundancy Removal during High-Level Synthesis Using Scheduling Don't-Cares. Search on Bibsonomy J. Electronic Testing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF scheduling dont-care, high-level synthesis, redundancy
40Giovanni De Micheli, David C. Ku HERCULES - a System for High-Level Synthesis. Search on Bibsonomy DAC The full citation details ... 1988 DBLP  BibTeX  RDF
40Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee Macro-models for high level area and power estimation on FPGAs. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF model, FPGA, high-level synthesis, power estimation, RTL, area estimation
40Rehab F. Abdel-Kader Resource-constrained loop scheduling in high-level synthesis. Search on Bibsonomy ACM Southeast Regional Conference (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF scheduling, high-level synthesis, force-directed scheduling
40María C. Molina, José M. Mendías, Román Hermida High-level synthesis of multiple-precision circuitsindependent of data-objects length. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF scheduling, high-level synthesis, allocation, multiple-precision
40Jayesh Siddhiwala, Liang-Fang Chao Scheduling conditional data-flow graphs with resource sharing. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF conditional data-flow graphs, resource sharing algorithm, pipeline scheduling algorithms, loop constructs, condition vector, dynamic resource sharing, rotation scheduling technique, parallel algorithms, data structures, data structure, resource allocation, high level synthesis, high level synthesis, processor scheduling, pipeline processing, data flow graphs, loop pipelining, conditional branches
40Mahsa Vahidi, Alex Orailoglu Testability metrics for synthesis of self-testable designs and effective test plans. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF testability metrics, self-testable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, built-in self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs
40Ivan P. Radivojevic, Forrest Brewer Analysis of conditional resource sharing using a guard-based control representation. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF conditional resource sharing, guard-based control representation, hardware resources optimisation, conditional data-flow graph behavior, cyclic loops, maximization of throughput, high level synthesis, high level synthesis, systems analysis, software pipelined, data flow graphs
40Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu Register binding for clock period minimization. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF high-level synthesis, clock skew, timing optimization
39Sreeranga P. Rajan, Masahiro Fujita Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Modeling, Formal Verification, ATM, Validation, High-Level Synthesis, VHDL
39Ganesh Lakshminarayana, Niraj K. Jha High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
39Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard SOMA: a tool for synthesizing and optimizing memory accesses in ASICs. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF high-level synthesis, memory synthesis
39Alex Doboli, Ranga Vemuri Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
39Daniel D. Gajski, Loganath Ramachandran Introduction to High-Level Synthesis. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
38Pradeep Prabhakaran, Prithviraj Banerjee Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF parallel algorithms, multiprocessors, High-level synthesis, network of workstations, hierarchical graphs, force-directed scheduling
38Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin 0001 Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. Search on Bibsonomy Signal Processing Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Prototyping, Refinement, High-level synthesis, Design space exploration, System level design
38Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee Leakage power optimization with dual-Vth library in high-level synthesis. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF dual-Vth, optimization, high-level synthesis, leakage power
38Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF lifecycle analysis, register optimization, high-level synthesis, hardware description languages, Behavioral synthesis, hierarchical specifications
38Apostolos A. Kountouris, Christophe Wolinski Efficient scheduling of conditional behaviors for high-level synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF conditional behavior, scheduling, high level synthesis (HLS), Design automation
38Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta 0001, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF common sub-expression elimination, dynamic CSE, parallelizing transformations, high-level synthesis
38Giri Tiruvuri, Moon Chung Estimation of lower bounds in scheduling algorithms for high-level synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF lower-bound estimated, scheduling, dynamic programming, high-level synthesis
38Anna Antola, Vincenzo Piuri, Mariagiovanna Sami High-level Synthesis of Data Paths with Concurrent Error Detection. Search on Bibsonomy DFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF self-checking systems, high-level synthesis, concurrent error detection, data path
38Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau Exploiting off-chip memory access modes in high-level synthesis. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF High Level Synthesis, DRAM, Memory Synthesis
38Minjoong Rim, Rajiv Jain Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF super-scalar, loop compilation, High-level synthesis, VLIW, loop transformations, loop optimization, pipeline scheduling
38Yung-Ming Fang, D. F. Wong Multiplexor Network Generation in High Level Synthesis. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF High Level Synthesis
38Krzysztof Kuchcinski Constraints-driven scheduling and resource assignment. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF scheduling, high-level synthesis, Constraint programming, system-level synthesis, resource assignment
37Jem Daalder, Peter W. Eklund, Kenji Ohmori High-Level Synthesis Optimization with Genetic Algorithms. Search on Bibsonomy PRICAI The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
37Peter Lisherness, Kwang-Ting (Tim) Cheng SCEMIT: a systemc error and mutation injection tool. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF high-level synthesis, coverage, SystemC, mutation
37Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
37Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng Bitwidth-aware scheduling and binding in high-level synthesis. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
37Zhang Yang, Rajesh K. Gupta 0001 A Case Analysis of System Partitioning and Its Relationship To High-Level Synthesis Tasks. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
36Sumit Gupta, Nicolae Savoiu, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau Using global code motions to improve the quality of results for high-level synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36Raghava V. Cherabuddi, Magdy A. Bayoumi, H. Krishnamurthy A low power based system partitioning and binding technique for multi-chip module architectures. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF binding technique, multi-chip module architectures, high-level synthesis framework, inter-chip buses, stochastic evolution based technique, multichip modules, switching activity, MCM, functional units, system partitioning, benchmark designs
36Chih-Tung Chen, Kayhan Küçükçakar High-level scheduling model and control synthesis for a broad range of design applications. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
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