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article(1090) incollection(11) inproceedings(3481) phdthesis(21) proceedings(22)
Venues (Conferences, Journals, ...)
SLIP(260) IEEE Trans. on CAD of Integrat...(249) DAC(236) IEEE Trans. VLSI Syst.(188) ICCAD(169) ISQED(138) DATE(135) ASP-DAC(122) VLSI Design(102) ISPD(95) IPDPS(92) ISCAS(90) ACM Great Lakes Symposium on V...(87) FPGA(81) ICCD(76) ITC(60) More (+10 of total 639)
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Found 4625 publication records. Showing 4625 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
92Narender Hanchate, Nagarajan Ranganathan A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay
91Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix Prediction of interconnect adjacency distribution: derivation, validation, and applications. Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF interconnect adjacency, interconnect pattern density, prediction, stochastic model, probability density function
81Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester The great interconnect buffering debate: are you a chicken or an ostrich? Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
79Ian O'Connor Optical solutions for system-level interconnect. Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF interconnect technology, optical network on chip, optical interconnect
75Marvin Tom, David Leong, Guy G. Lemieux Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
75Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF interconnect power, piecewise model, slack
74Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright Prediction of interconnect pattern density distribution: derivation, validation, and applications. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF interconnect network prediction, interconnect pattern density, Stochastic model, probability density function
73Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex Global interconnect trade-off for technology over memory modules to application level: case study. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect
68Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson 0001, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi Predictions of CMOS compatible on-chip optical interconnect. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CMOS compatible, on-chip, optical interconnect, trends
67Jian Liu, Meigen Shen, Li-Rong Zheng 0001, Hannu Tenhunen System level interconnect design for network-on-chip using interconnect IPs. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF interconnect IP, network on chip, interconnect, bandwidth optimization
63Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma Interconnect Tuning Strategies for High-Performance Ics. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
63Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi Time-Domain Simulation of Variational Interconnect Models. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF simulation, Interconnect, variational models, reduced order modeling
63Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer Interconnect power and delay optimization by dynamic programming in gridded design rules. Search on Bibsonomy ISPD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization
63Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect
63Narender Hanchate, Nagarajan Ranganathan Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Game theory, gate sizing, transmission lines, crosstalk noise, interconnect models, interconnect delay
62Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alexandre Yakovlev, Gordon Russell The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk. Search on Bibsonomy SLIP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF cross-talk, interconnect, variability, Bit Error Rate(BER)
62Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir Interconnect-power dissipation in a microprocessor. Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF interconnect power, wire spacing, routing, low-power design
62Michael D. Hutton Interconnect prediction for programmable logic devices. Search on Bibsonomy SLIP The full citation details ... 2001 DBLP  DOI  BibTeX  RDF interconnect prodiction, wireability, architecture, programmable logic device
62Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne Burleson NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF on-chip, spice-based, network-on-chip, interconnects, signaling
61Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex Interconnect exploration for future wire dominated technologies. Search on Bibsonomy SLIP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF interconnect wire processing, intra/inter-memory interconnect, pareto-optimal energy/delay interconnect exploration
58Jian Li, Rajesh K. Gupta 0001 An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
58Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester Improved a priori interconnect predictions and technology extrapolation in the GTX system. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
58Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi High-level synthesis under multi-cycle interconnect delay. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
58James D. Meindl XXI Century Gigascale Integration (GSI) : The Interconnect Problem. Search on Bibsonomy ARVLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
57Andrew B. Kahng, Kei Masuko, Sudhakar Muddu Analytical delay models for VLSI interconnects under ramp input. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
57Yehia Massoud, Arthur Nieuwoudt Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits. Search on Bibsonomy JETC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF nanotube bundle, interconnect, inductance, Carbon nanotube, resistance
57Md. Sajjad Rahaman, Masud H. Chowdhury Improved ber performance in intra-chip rf/wireless interconnect systems. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF RF interconnect, intra-chip channel, wireless interconnect, interleaver, error control coding, channel coding
57Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy, Abhijit Mahajan VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF VLSI photonics, signal processing performance, multicomputer interconnect architecture, optical interconnect
57Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh A Scalable Communication-Centric SoC Interconnect Architecture. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure
56Arthur Nieuwoudt, Yehia Massoud Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Mutli-walled carbon nanotubes, nanotube interconnect, interconnect, interconnect reliability
56Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF moment-matching methods, passive interconnect macromodeling, descriptor form, passive model order reduction, projection-based truncated balanced realization method, large RLC interconnect circuits, Lur'e equation, algebraic Riccati equations, generalized Lyapunov equations, passivity preservation, congruence transformation, large scale interconnect circuit, linear systems, structure information, Krylov-subspace methods, block structure, balanced truncation
56Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect
56Bill R. Bottoms Interconnect solutions for TeraScale computing. Search on Bibsonomy SLIP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF interconnect
56Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu Is overlay error more important than interconnect variations in double patterning? Search on Bibsonomy SLIP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF double patterning lithography, interconnect variations, overlay
56Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester Investigation of performance metrics for interconnect stack architectures. Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF back-end metrics, interconnect stacks, via blockage, throughput, energy, bandwidth
56Wim Heirman, Joni Dambre, Jan Van Campenhout Synthetic traffic generation as a tool for dynamic interconnect evaluation. Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF dynamic interconnect requirements, reconfigurable interconnect, synthetic traffic generation
56Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex Impact of interconnect resistance increase on system performance of low power and high performance designs. Search on Bibsonomy SLIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing
56Jens Lienig Interconnect and current density stress: an introduction to electromigration-aware design. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF interconnect, layout, physical design, electromigration, current density, interconnect reliability
52Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera Worst-case delay analysis considering the variability of transistors and interconnects. Search on Bibsonomy ISPD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF worst-case delay, interconnect, process variation
52Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai Inductance extraction for general interconnect structures. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Geetanjali Kshirsagar, Masud H. Chowdhury Optical Interconnect Technology; Photons Based Signal Communication. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Fei Li 0003, Yan Lin 0001, Lei He 0001 Vdd programmability to reduce FPGA interconnect power. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
52Navaratnasothie Selvakkumaran, Phiroze N. Parakh, George Karypis Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF interconnection complexity, multilevel global placement, nonhomogeneity, perimeter-degree, congestion, routability
52Akis Doganis Interconnect Statistical Modeling: Structures and Measurement Methodologies. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
52Jianmin Li, Chung-Kuan Cheng Routability improvement using dynamic interconnect architecture. Search on Bibsonomy FCCM The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
51Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore An intra-chip free-space optical interconnect. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF free-space optical interconnect, intra-chip, 3d
51Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. N. Srikant INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations. Search on Bibsonomy CASES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF interconnect, energy modeling, energy-aware scheduling, clustered VLIW processors
51Neal K. Bambha, Shuvra S. Bhattacharyya Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF scheduling, task graphs, interconnect synthesis, Embedded multiprocessors
51Ankireddy Nalamalpu, Wayne Burleson Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters. Search on Bibsonomy ISPD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF methodology, timing, interconnect, buffering
51Ian G. Harris, Russell Tessier Interconnect testing in cluster-based FPGA architectures. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF field-programmable gate arrray, interconnect testing, hierarchical test
51Chen-Huan Chiang, Sandeep K. Gupta BIST TPG for SRAM cluster interconnect testing at board level. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
51Andrew B. Kahng, Bao Liu, Xu Xu 0001 Statistical crosstalk aggressor alignment aware interconnect delay calculation. Search on Bibsonomy SLIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
51N. P. van der Meijs, T. Smedes Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Physical Design Verification, Interconnect Resistance Extraction, Interconnect Capacitance Extraction, Substrate Resistance Extraction, Interconnect Modeling
51Yu Hu, King Ho Tam, Tong Jing, Lei He 0001 Fast dual-vdd buffering based on interconnect prediction and sampling. Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF routing, low power, interconnect, buffer insertion, dual-Vdd
51Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF wire-length distribution model, routing, interconnect, rent
51Vikas Chandra, Anthony Xu, Herman Schmit A low power approach to system level pipelined interconnect design. Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF pipelined interconnect, low power, voltage scaling
51Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex Interconnect width selection for deep submicron designs using the table lookup method. Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF interconnect sizing, power-delay trade-off, wire sizing
51Ajay Joshi, Jeffrey A. Davis A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF interconnect area, wire sharing, time-division multiplexing
51Shankar Balachandran, Dinesh Bhatia A-priori wirelength and interconnect estimation based on circuit characteristics. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF routing demand, placement, wirelength, interconnect estimation
51Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham A hierarchical three-way interconnect architecture for hexagonal processors. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Y architecture, Y tree, interconnect architecture
51Chao-Yang Yeh, Malgorzata Marek-Sadowska Sequential delay budgeting with interconnect prediction. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF delay budgeting, sequential circuits, interconnect prediction
51Phillip Christie, José Pineda de Gyvez Pre-layout prediction of interconnect manufacturability. Search on Bibsonomy SLIP The full citation details ... 2001 DBLP  DOI  BibTeX  RDF design, reliability, interconnect, theory, yield, Rent's rule, critical areas
50Wenyi Feng, Jonathan W. Greene Post-placement interconnect entropy: how many configuration bits does a programmable logic device need? Search on Bibsonomy SLIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF switching requirement, FPGAs, lower bound, entropy, interconnect, placement, rent's rule, programmable interconnect
46Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley Efficient tiling patterns for reconfigurable gate arrays. Search on Bibsonomy FPGA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA hexagonal octagonal, tiling interconnect
46Chiu-Wing Sham, Evangeline F. Y. Young Area reduction by deadspace utilization on interconnect optimized floorplan. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF area reduction, Floorplanning
46Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud Assessing carbon nanotube bundle interconnect for future FPGA architectures. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David T. Blaauw Statistical interconnect metrics for physical-design optimization. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
46Vishal Suthar, Shantanu Dutt Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
46N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell Benchmarks for Interconnect Parasitic Resistance and Capacitance. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
46John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
46Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas Impact of interconnect variations on the clock skew of a gigahertz microprocessor. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
46Frank W. Angelotti Generating interconnect models from prototype hardware. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
46Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
46Tai A. Ly, W. Lloyd Elwood, Emil F. Girczyc A Generalized Interconnect Model for Data Path Synthesis. Search on Bibsonomy DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
46Joshua Hursey, Timothy Mattox, Andrew Lumsdaine Interconnect agnostic checkpoint/restart in open MPI. Search on Bibsonomy HPDC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF checkpoint coordination protocol, fault tolerance, MPI, shared memory, rollback-recovery, infiniband, myrinet, high speed interconnect, checkpoint/restart
46Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Interconnect-Aware Design, Low Power, Processor Architecture, Energy-Aware Design
46Frank Huebbers, Ali Dasdan, Yehea I. Ismail Computation of accurate interconnect process parameter values for performance corners under process variations. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF sorners, delay, interconnect, STA, variations
46Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck Exploration of pipelined FPGA interconnect structures. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF PipeRoute, pipelined FPGA, pipelined interconnect, registered routing, architecture explorations
46Shalini Ghosh, F. Joel Ferguson Estimating detection probability of interconnect opens using stuck-at tests. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF break fault, interconnect open, stuck-at test
46Kavel M. Büyüksahin, Farid N. Najm High-level power estimation with interconnect effects. Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF high-level power estimation, interconnect capacitance estimation, register transfer level (RTL) power estimation
45Qinwei Xu, Pinaki Mazumder Novel interconnect modeling by using high-order compact finite difference methods. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF differential quadrature method, discrete interconnect modeling, passivity, interconnect modeling, transient simulation
45Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan Global interconnect sizing and spacing with consideration of coupling capacitance. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
45Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. Search on Bibsonomy SLIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45N. S. Nagaraj Dealing with interconnect process variations. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny Timing optimization in logic with interconnect. Search on Bibsonomy SLIP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF interconnect, logic circuits, timing optimization, repeaters, logical effort
45Andrew B. Kahng, Rasit Onur Topaloglu Generation of design guarantees for interconnect matching. Search on Bibsonomy SLIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF design guarantee generation, interconnect matching
45Viet H. Nguyen, Phillip Christie The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF interstratal interconnect, 3D-IC, system-level
45Luca Daniel, Chin Siong Ong, Sok Chay Low, Kwok Hong Lee, Jacob White Geometrically parameterized interconnect performance models for interconnect synthesis. Search on Bibsonomy ISPD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF parametrized model order reduction, interconnect synthesis
45Ingrid Verbauwhede, M.-C. Frank Chang Reconfigurable interconnect for next generation systems. Search on Bibsonomy SLIP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF architectures, reconfiguration, interconnect, design methods, power efficiency
44David Yeager, Darius Chiu, Guy G. Lemieux Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF congestion estimation, congestion localization, interconnect prediction, FPGA routing, FPGA interconnect
44Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand Impact of interconnect length changes on effective materials properties (dielectric constant). Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF performance, routing, interconnect, cycle time, interconnect model, rent, path delay
44Dennis Sylvester Measurement techniques and interconnect estimation. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF capacitance measurement, interconnect characterization, noise measurement, process variation, interconnect estimation
41Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Qi Zhu 0002, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang 0040 Spanning graph-based nonrectilinear steiner tree algorithms. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
41Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF interconnect, power, SMP, cache coherence protocol
40Manuel Sellier, Jean Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Predictive SPICE Modeling, Interconnect Resistance, Buffer Insertion, Interconnect Delay
40Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
40Jifeng Chen, Jin Sun, Janet Meiling Wang Robust interconnect communication capacity algorithm by geometric programming. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF communication capacity, optimization, robust, uncertainty, process variation, geometric programming, ellipsoid
40Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton Practical Asynchronous Interconnect Network Design. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
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