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Found 124 publication records. Showing 124 according to the selection in the facets
Hits ?▲ 
Authors 
Title 
Venue 
Year 
Link 
Author keywords 
15  Masayuki Tsukisaka, Takashi Nanya 
A testable design for asynchronous finegrain pipeline circuits. 
PRDC 
2000 
DBLP DOI BibTeX RDF 
asynchronous finegrain pipeline circuits, dynamic gates, highperformance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design 
15  Lijian Li, Xiaoyang Yu, ChengWen Wu, Yinghua Min 
A waveform simulator based on Boolean process. 
Asian Test Symposium 
2000 
DBLP DOI BibTeX RDF 
waveform simulator, high performance integrated circuits, Boolean functions, logic CAD, timing behavior, Boolean process 
15  Andrzej Hlawiczka, Michal Kopec 
Design and testing of fast and cost effective serial seeding TPGs based on onedimensional linear hybrid cellular automata. 
Asian Test Symposium 
2000 
DBLP DOI BibTeX RDF 
serial seeding, linear hybrid cellular automata, ncell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, nbit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flipflops, flipflops, shift registers, pattern generators, integrated circuit economics 
15  Elizabeth M. Rudnick, Janak H. Patel 
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. 
VLSI Design 
1997 
DBLP DOI BibTeX RDF 
serial logic simulation bottleneck, parallel fault simulation, sequential circuit fault simulation algorithms, faultpartitioning approach, test set partitioning, parallel architectures, logic CAD, fault coverage, speedup, benchmark circuits 
15  Karen Panetta Lentz, Elias S. Manolakos, Edward C. Czeck 
A multiple domain environment for efficient simulation. 
Annual Simulation Symposium 
1997 
DBLP DOI BibTeX RDF 
multiple domain environment, efficient simulation, concurrent simulation methodology, digital logic experimentation, multiple experiment environment, independent experiments, parallel hardware, digital logic simulators, signature paths, multiple experiment algorithms, function list, dynamic interactions, exhaustive simulation problem, Multiple Stuckat Fault simulations, logic CAD, coverage analysis, digital logic 
15  ShiYu Huang, KuangChien Chen, KwangTing Cheng 
Incremental logic rectification. 
VTS 
1997 
DBLP DOI BibTeX RDF 
incremental logic rectification, incorrect combinational circuit, symbolic BDD techniques, sequence of partial corrections, circuits with multiple errors, general singlegate correction, structural correspondence, ISCAS85 benchmark circuits, error region pruning, specification, implementation, logic CAD, VLSI design, hybrid approach 
15  Zhanping Chen, Kaushik Roy 0001, TanLi Chou 
Power sensitivity  a new method to estimate power dissipation considering uncertain specifications of primary inputs. 
ICCAD 
1997 
DBLP DOI BibTeX RDF 
Monte Carlo based approach, maximum bounds, minimum bounds, power dissipation estimation, power sensitivity, primary inputs, signal properties, signal switching, uncertain specifications, logic CAD, CMOS logic circuits, power estimation, CMOS circuits, signal probability, statistical technique 
15  Patrick Vuillod, Luca Benini, Giovanni De Micheli 
Generalized matching from theory to application. 
ICCAD 
1997 
DBLP DOI BibTeX RDF 
MCNC 91 benchmark suite, algorithmic optimization, generalized matching, library cells, multioutput network, postmapping optimization, unconstrained delay minimization, logic CAD, power minimization, delay constraints, area minimization, Boolean relation 
15  ChiHong Hwang, Allen C.H. Wu 
A predictive system shutdown method for energy saving of eventdriven computation. 
ICCAD 
1997 
DBLP DOI BibTeX RDF 
VLSI circuit design, delay overhead, eventdriven computation, exponentialaverage approach, low delay penalties, prewakeup, predictionmiss correction, predictive system shutdown method, sleep mode operations, systemlevel power management, VLSI, finite state machine, logic CAD, energy saving, power saving, hit ratio, idle period 
15  Vi Chi Chan, David Lewis 
Hierarchical partitioning for fieldprogrammable systems. 
ICCAD 
1997 
DBLP DOI BibTeX RDF 
FPGA partitioning problems, circuit structures, fieldprogrammable systems, partitioning tree, recursive bipartitioning algorithm, field programmable gate arrays, VLSI, quality, logic CAD, hierarchical partitioning 
15  Peggy B. K. Pang, Mark R. Greenstreet 
SelfTimed Meshes Are Faster Than Synchronous. 
ASYNC 
1997 
DBLP DOI BibTeX RDF 
selftimed meshes, linear speedup, perprocessor performance, simulation, logic CAD 
15  Sumit Roy 0003, Prithviraj Banerjee 
A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis. 
IPPS 
1997 
DBLP DOI BibTeX RDF 
algebraic factorization, circuit replication, totally independent factorization, Lshaped partitioning strategy, rectangle interaction, ex1010 circuit, sequential kernel extraction algorithms, SIS sequential circuit synthesis system, quality degradation, parallel algorithms, logic synthesis, logic CAD, circuit partitions, divideandconquer strategy 
15  Jaswinder Pal Singh, A. Kumar, Sanjeev Kumar 
A multiplier generator for Xilinx FPGAs. 
VLSI Design 
1996 
DBLP DOI BibTeX RDF 
multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs 
15  Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal 
Parallel concurrent pathdelay fault simulation using singleinput change patterns. 
VLSI Design 
1996 
DBLP DOI BibTeX RDF 
concurrent pathdelay fault simulation, singleinput change patterns, singlytestable pathdelay faults, random values, rising transitions, falling transitions, sixteenvalued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flipflops, Boolean operations 
15  Arun Balakrishnan, Srimat T. Chakradhar 
Retiming with logic duplication transformation: theory and an application to partial scan. 
VLSI Design 
1996 
DBLP DOI BibTeX RDF 
logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flipflops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flipflops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function 
15  Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal 
Improving accuracy in path delay fault coverage estimation. 
VLSI Design 
1996 
DBLP DOI BibTeX RDF 
fault coverage estimation, simulated vector pair, exact fault simulation, fixedlength pathsegments, fanin branches, fanout branches, flagged pathsegments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time 
15  S. Sundaram, Lalit M. Patnaik 
Distributed logic simulation: timefirst evaluation vs. event driven algorithms. 
VLSI Design 
1996 
DBLP DOI BibTeX RDF 
distributed logic simulation, timefirst evaluation algorithm, event driven algorithm, digital circuit simulation, distributed simulation algorithms, parallel algorithms, parallel processing, VLSI, logic CAD, circuit analysis computing, integrated logic circuits, VLSI circuits, parallel logic simulation 
15  Prathima Agrawal, B. Narendran, Narayanan Shivakumar 
Multiway partitioning of VLSI circuits. 
VLSI Design 
1996 
DBLP DOI BibTeX RDF 
multiway partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric 
15  Julien Dunoyer, Nizar Abdallah, Pirouz BazarganSabet 
A symbolic simulation approach in resolving signals' correlation. 
Annual Simulation Symposium 
1996 
DBLP DOI BibTeX RDF 
signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools 
15  Ayman I. Kayssi 
Macromodeling C and RCloaded CMOS inverters for timing analysis. 
Great Lakes Symposium on VLSI 
1996 
DBLP DOI BibTeX RDF 
RCloaded CMOS inverters, Cloaded CMOS inverters, seriesresistor shuntcapacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling 
15  Come Rozon 
On the Use of VHDL as a MultiValued Logic Simulator. 
ISMVL 
1996 
DBLP DOI BibTeX RDF 
multivalued logic simulator, ternary circuits, simulation, VHDL, logic CAD, functionality, circuit analysis computing, hardware description languages, digital circuits, multivalued logic circuits, timing specifications 
15  Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda 
Scan insertion criteria for low design impact. 
VTS 
1996 
DBLP DOI BibTeX RDF 
scan insertion criteria, design impact, flipflop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flipflops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan 
15  Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska 
Design and performance of CMOS TSPC cells for high speed pseudo random testing. 
VTS 
1996 
DBLP DOI BibTeX RDF 
CMOS TSPC cells, high speed pseudo random testing, builtin selftest scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, builtin self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists 
15  Wanlin Cao, Dhiraj K. Pradhan 
Sequential redundancy identification using recursive learning. 
ICCAD 
1996 
DBLP DOI BibTeX RDF 
ISCAS benchmarks, ccycle redundancies, ccycle redundant faults, redundancy identification algorithm, sequential redundancy identification, state transition information, uncontrollability analysis, logic CAD, FIRES, untestable faults, recursive learning 
15  Christoph Schaffer 
Hierarchical architectural design, simulation and evaluation. 
ECBS 
1996 
DBLP DOI BibTeX RDF 
hierarchical architectural design, computer design evaluation, tool environment, multistrata systems, multilayer systems, performance evaluation, virtual machines, requirements, computer architecture, logic CAD, system engineering, computer simulation, system theory, system theory, tradeoff analysis, architectural design decisions 
15  Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri 
Technology mapping on a multioutput logic module built around Cellular Automata Array for a new FPGA architecture. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
multioutput logic module, cellular automata array, design turnaround time, field programmability, rapid circuit realization, logic blocks, ANDXOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture 
15  S. C. Prasad, Kaushik Roy 0001 
Circuit optimization for minimisation of power consumption under delay constraint. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
power consumption minimisation, internal capacitances, seriesconnected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates 
15  Manjit Borah, Mary Jane Irwin, Robert Michael Owens 
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
power consumption minimisation, static CMOS circuits, input reordering, high fanout gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing 
15  Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross 
Efficient variable ordering and partial representation algorithm. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
partial representation algorithm, ordered partial decision diagrams, informationtheoretic criteria, CAD problems, VLSI, data structures, data structures, entropy, Boolean functions, Boolean function, logic CAD, BDDs, variable ordering, truth table 
15  Chunduri Rama Mohan, Partha Pratim Chakrabarti 
Combined optimization of area and testability during state assignment of PLAbased FSM's. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
combined optimization, testability optimisation, PLAbased FSM, EARTH algorithm, single crosspoint faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuckat faults, area minimization 
15  Arun Balakrishnan, Srimat T. Chakradhar 
Partial scan design for technology mapped circuits. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
technology mapped circuits, scan flipflops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flipflops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design 
15  A. Pal, R. K. Gorai, V. V. S. S. Raju 
Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach 
15  Srimat T. Chakradhar 
Optimum retiming of large sequential circuits. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flipflops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation 
15  Khushro Shahookar, Pinaki Mazumder 
Genetic multiway partitioning. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
genetic multiway partitioning, result quality, binary chromosome, bitmask operations, net cut evaluation, MCNC benchmark circuits, cut size, genetic algorithms, VLSI, VLSI, CAD, software tools, software tool, logic CAD, mutation, circuit CAD, crossover, cellular arrays, cost function, circuit optimisation, logic partitioning, multiple objectives, bipartitioning 
15  Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli 
A new switchinglevel approach to multipleoutput functions synthesis. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
switchinglevel, multipleoutput functions synthesis, transistor level, randomly generated functions, logic CAD, timing constraints, circuit layout CAD, CMOS logic circuits, multivalued logic circuits, integrated circuit layout, minimisation of switching nets, area minimization, figures of merit 
15  Raj S. Mitra, Partha S. Roop, Anupam Basu 
Implementation of design functions by available devices: a new algorithm. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
design functions, available devices, function behaviors, mapping process, VLSI, VLSI, CAD, finite state machines, finite state machines, logic CAD, circuit CAD, logic partitioning, logic partitioning 
15  Mahesh Mehendale, M. K. Ram Prasad 
AATMA: an algorithm for technology mapping for antifusebased FPGAs. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
AATMA, antifusebased FPGAs, logic module structure, complex functions, signaturematching based approach, mapping quality, logic module architectures, field programmable gate arrays, directed graphs, combinational circuits, logic CAD, technology mapping, execution times 
15  Sven Simon 0001, Ralf Bucher, Josef A. Nossek 
Retiming of synchronous circuits with variable topology. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits 
15  U. K. Bhattacharyya, I. Sen Gupta, S. Shyama Nath, P. Dutta 
PLA based synthesis and testing of hazard free logic. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multioutput circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions 
15  Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher 
Comparison of the layout synthesis of radix2 and pseudoradix4 dividers. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
layout synthesis, radix2 dividers, pseudoradix4 dividers, redundant number notation, carrypropagationfree addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digitrecurrence division 
15  William L. Bradley, Ranga Vemuri 
Transformations for functional verification of synthesized designs. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
lowlevel functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, dephase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states 
15  Luca Penzo, Donatella Sciuto, Cristina Silvano 
VLSI design of systematic oddweightcolumn byte error detecting SECDED codes. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
oddweightcolumn byte error detection, SECDED codes, single error correction, double error detection, single byte error detection, SECDEDSBD codes, high performances VLSI implementations, high speed encoding/decoding circuits, parallel data manipulation, VHSIC Hardware Description Language, VHDL description, parallel processing, VLSI, software tool, error correction codes, application specific integrated circuits, logic CAD, decoding, VLSI design, error detection codes, hardware description languages, integrated logic circuits, digital integrated circuits 
15  C. Rominger, Jean Claude Geffroy 
Hazard analysis of structured sequential systems. 
Annual Simulation Symposium 
1995 
DBLP DOI BibTeX RDF 
structured sequential systems, time uncertainties, asynchronous sequential systems, nondeterministic phenomena, simulation method, structured systems, fault diagnosis, CAD, logic testing, timing, sequential circuits, logic CAD, asynchronous circuits, digital simulation, time analysis, circuit analysis computing, hazard analysis, asynchronous sequential logic 
15  Glenn Jennings 
Accurate ternaryvalued compiled logic simulation of complex logic networks by OTDD composition. 
Annual Simulation Symposium 
1995 
DBLP DOI BibTeX RDF 
circuit diagrams, ternaryvalued compiled logic simulation, complex logic networks, OTDD composition, combinational U inaccuracies, reconvergent fanout, Kleenean strong ternary logic, Ordered Ternary Decision Diagram, standard ISCAS 85 benchmarks, performance evaluation, logic CAD, digital simulation, circuit analysis computing, ternary logic, incompletelyspecified functions 
15  Krishna Kant 
Performance of internal overload controls in large switches. 
Annual Simulation Symposium 
1995 
DBLP DOI BibTeX RDF 
internal overload control performance, large switches, switch sizes, call capacity, voice circuits, overload performance, network integrity, peripheral scanning schemes, scheduling, performance evaluation, virtual machines, logic CAD, circuit analysis computing, simulation model, service integrity, buffer sizes, switching circuits 
15  Youngmin Hur, Stephen A. Szygenda 
Special purpose array processor for digital logic simulation. 
Annual Simulation Symposium 
1995 
DBLP DOI BibTeX RDF 
special purpose array processor, digital logic simulation, large VLSI circuits, computeintensive tasks, digital analysis, time driven array processor, massively parallel processing element, compiled eventdriven technology, nominal transport delay timing analysis, delay time order, levelized circuit, massively parallel PE array, MARS accelerator, VLSI, parallel architectures, delays, timing, fault simulation, logic CAD, digital simulation, circuit analysis computing, special purpose computers, SIMD architecture, hardware cost 
15  Uwe Hinsberger, Reiner Kolla 
Optimal technology mapping for single output cells. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
optimal technology mapping, single output cells, DAGmapping, minimum delay mapping, duplicationfree mapping, logic duplication, ATtradeoffs, LUTFPGAs, field programmable gate arrays, delays, Boolean functions, Boolean functions, logic CAD, table lookup, cost functions, circuit optimisation, lookup table 
15  Joseph L. Ganley, James P. Cohoon 
Thumbnail rectilinear Steiner trees. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
fullset decomposition algorithm, minimumlength set, thumbnail rectilinear Steiner tree problem, VLSI placement algorithms, geometric partitioning, field programmable gate arrays, fieldprogrammable gate arrays, VLSI, dynamic programming, network topology, logic CAD, trees (mathematics), network routing, circuit layout CAD, global routing, line segments 
15  Habib Youssef, Sadiq M. Sait, Khaled Nassar, Muhammad S. T. Benten 
Performance driven standardcell placement using the genetic algorithm. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
connection length, timingdriven placer, /spl alpha/criticality, delay performance improvement, genetic algorithms, genetic algorithm, delays, timing, logic CAD, circuit layout CAD, cellular arrays, integrated circuit layout, critical paths, area, propagation delays, wire length, timing performance, IC design, standardcell placement 
15  Harry Hollander, Bradley S. Carlson, Toby D. Bennett 
Synthesis of SEUtolerant ASICs using concurrent error correction. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
radiation hardening (electronics), SEUtolerant ASIC synthesis, single error correction/double error detection Hamming code, delay overhead, memory element set partitioning, error correction codes, sequential circuits, sequential circuit, application specific integrated circuits, logic CAD, circuit layout CAD, single event upsets, logic partitioning, Hamming codes, fault tolerant design, area overhead, memory elements, design experiments, concurrent error correction 
15  M. J. van der Westhuizen, R. G. Harley, D. C. Levy, D. R. Woodward 
Using EDIF for software generation. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
EDIF, parallel microprocessors, codesign methods, hardware development tools, realtime parallel C code, FPGA, parallel programming, simulated annealing, simulated annealing, software tools, software tool, logic CAD, circuit CAD, C language, scheduling theory, software generation, development systems 
15  Dimitrios Karayiannis, Spyros Tragoudas 
Uniform area timingdriven circuit implementation. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
circuit module, cell library, inputoutput paths, overall area, timingdriven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NPhard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay 
15  Stanley Habib, Quan Xu 
Technology mapping algorithms for sequential circuits using lookup table based FPGAS. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flipflops, flipflops, circuit layout CAD, table lookup, time delay, lookup table 
15  Enrico Macii, Massimo Poncino 
Estimating worstcase power consumption of CMOS circuits modeled as symbolic neural networks. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
worstcase power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation 
15  Michael Sheliga, Edwin HsingMean Sha 
Bus minimization and scheduling of multichip systems. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
bus minimization, multichip module design, scheduling, scheduling, logic CAD, polynomial time algorithm, circuit layout CAD, multichip modules, signal flow graphs, signal flow graphs, algorithm efficiency 
15  Garth Baulch, David Hemmendinger, Cherrice Traver 
Analyzing and verifying locally clocked circuits with the concurrency workbench. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
locally clocked circuits, concurrency workbench, synchronous computational elements, concurrent system modelling, CCS process algebra, formal verification, timing, logic design, process algebra, logic CAD, asynchronous circuits, asynchronous circuits, circuit analysis computing, asynchronous communication 
15  Enric Pastor, Jordi Cortadella, Oriol Roig 
A new look at the conditions for the synthesis of speedindependent circuits. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
gatelevel synthesis, gate library constraint, fanin reduction, VLSI, logic design, logic CAD, integrated circuit design, circuit CAD, integrated logic circuits, circuit optimisation, optimization techniques, speedindependent circuits 
15  Nestoras Tzartzanis, William C. Athas 
Design and analysis of a lowpower energyrecovery adder. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
energyrecovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation 
15  Frank Poirot, Gerard Tarroux, Ramine Roane 
Optimization using implicit techniques for industrial designs. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
implicit techniques, Boolean functions, Boolean functions, logic synthesis, logic CAD, binary decision diagrams, hardware description languages, hardware description languages, industrial designs, circuit optimisation, optimization techniques, design complexity 
15  JaeTack Yoo, Erik Brunvand, Kent F. Smith 
Automatic rapid prototyping of semicustom VLSI circuits using Actel FPGAs. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cellmatrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC 
15  Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo 
A soft computing approach to hardware software codesign. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
soft computing approach, partitioning phase, genetic algorithms, genetic algorithms, fuzzy logic, fuzzy logic, logic CAD, computer aided software engineering, hardware/software codesign 
15  Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin 
Partitioning transition relations efficiently and automatically. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
automatic partitioning, state transition relations, abstract implicit state enumeration procedure, automatic verification method, graph theory, finite state machines, logic CAD, state estimation, logic partitioning, extended finite state machines, register transfer level designs, multiway decision graphs 
15  Pai H. Chou, Ross B. Ortega, Gaetano Borriello 
The Chinook hardware/software cosynthesis system. 
ISSS 
1995 
DBLP DOI BibTeX RDF 
Chinook hardware/software cosynthesis system, custom logic, design cosimulation, design time constraints, embedded controller design, errorprone tasks, function migration, interface hardware, interface software, system components integration, realtime systems, software tools, logic design, microprocessors, logic CAD, microcontrollers, computeraided design tools 
15  Sanjay Rekhi, J. Donald Trotter 
HAL: heuristic algorithms for layout synthesis. 
ARVLSI 
1995 
DBLP DOI BibTeX RDF 
layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 11/2d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area 
15  Louis Monier, Ramsey W. Haddad, Jeremy Dion 
Recursive layout generation. 
ARVLSI 
1995 
DBLP DOI BibTeX RDF 
BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, handdrawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration 
15  Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng 
Automatic synthesis of gatelevel timed circuits with choice. 
ARVLSI 
1995 
DBLP DOI BibTeX RDF 
gatelevel timed circuits, Celements, explicit timing information, textual specification, conditional operation, reachable state space, semicustom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standardcells, CAD tool, automatic synthesis, gatearrays, statespace methods, AND gates, OR gates 
15  Scott Hauck, Gaetano Borriello 
An evaluation of bipartitioning techniques. 
ARVLSI 
1995 
DBLP DOI BibTeX RDF 
bipartitioning techniques, VLSI, logic CAD, integrated circuit design, circuit CAD, logic partitioning, logic partitioning, VLSI CAD 
15  Mahsa Vahidi, Alex Orailoglu 
Testability metrics for synthesis of selftestable designs and effective test plans. 
VTS 
1995 
DBLP DOI BibTeX RDF 
testability metrics, selftestable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, builtin self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs 
15  Nilanjan Mukherjee 0001, H. Kassab, Janusz Rajski, Jerzy Tyszer 
Arithmetic builtin self test for highlevel synthesis. 
VTS 
1995 
DBLP DOI BibTeX RDF 
arithmetic builtin self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, builtin self test, high level synthesis, highlevel synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage 
15  Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva 
A portable ATPG tool for parallel and distributed systems. 
VTS 
1995 
DBLP DOI BibTeX RDF 
portable ATPG tool, memory critical problems, electronic CAD, code portability, PVM library, DEC Alpha AXP, genetic algorithms, genetic algorithm, distributed systems, parallel architectures, parallel architectures, logic testing, message passing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, logic CAD, parallel systems, software portability, messagepassing libraries, CM5 
15  Xinli Gu 
RT level testabilitydriven partitioning. 
VTS 
1995 
DBLP DOI BibTeX RDF 
testabilitydriven partitioning, RT level designs, hardtotest points, testability analysis algorithm, normal mode, design function, test mode, acyclic partition, BIST technique, fault diagnosis, logic testing, builtin self test, integrated circuit testing, design for testability, ATPG, automatic testing, logic CAD, fault coverage, logic partitioning, test application time, data path, testability measurements, DFT techniques 
15  TingYu Kuo, ChunYeh Liu, Kewal K. Saluja 
An optimized testable architecture for finite state machines. 
VTS 
1995 
DBLP DOI BibTeX RDF 
optimized testable architecture, FSM synthesis, testable machine, transfer sequences, synthesis benchmark circuits, logic testing, finite state machines, finite state machines, sequential circuits, logic CAD, sequences, circuit optimisation, distinguishing sequences, synchronizing sequence 
15  Alessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò 
Reliability evaluation of combinational logic circuits by symbolic simulation. 
VTS 
1995 
DBLP DOI BibTeX RDF 
mcnc benchmark circuits, faulttolerant combinational logic circuits, circuit functionality, fault indicators, control variables, BDDbased symbolic simulation, undetectable multiple faults, VLSI, VLSI, combinational circuits, logic CAD, digital simulation, circuit analysis computing, reliability evaluation, integrated circuit reliability 
15  Alessandro Bogliolo, Maurizio Damiani 
Synthesis of combinational circuits with special faulthandling capabilitie. 
VTS 
1995 
DBLP DOI BibTeX RDF 
combinational circuit synthesis, faulthandling capabilities, internal faults, multilevel logic optimization process, logic testing, redundancy, redundancy, design for testability, logic design, combinational circuits, logic CAD, multivalued logic, circuit optimisation, selfchecking circuits, circuit reliability, faulttolerant circuits 
15  Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita 
Resynthesis for sequential circuits designed with a specified initial state. 
VTS 
1995 
DBLP DOI BibTeX RDF 
specified initial state, retiming method, redundancy removal method, resynthesized circuit, input sequences, logic optimisation, timing, redundancy, sequential circuits, logic CAD, flipflops, flipflops, circuit optimisation, synchronous sequential circuits 
15  Hirendu Vaishnav, Massoud Pedram 
Delay optimal partitioning targeting low power VLSI circuits. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
clustering, VLSI, partitioning, logic CAD, circuit CAD, integrated logic circuits, power dissipation, VLSI circuits, logic partitioning, delay optimal 
15  Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. SangiovanniVincentelli, Patrick Scaglia 
Fast discrete function evaluation using decision diagrams. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
address lookups, cyclebased logic simulation, decisiondiagram based function evaluation, fast discrete function evaluation, latch ports, ordersofmagnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multivalued decision diagrams 
15  TanLi Chou, Kaushik Roy 0001 
Statistical estimation of sequential circuit activity. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
Markov chain theory, sequential circuit activity, sequential logic circuits, signal activity, transient problem, sequential circuits, logic CAD, Monte Carlo, Monte Carlo methods, Monte Carlo technique 
15  Pranav Ashar, Sharad Malik 
Fast functional simulation using branching programs. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
compiled code simulation, cyclebased functional simulation, fast functional simulation, functional delayindependent logic simulation, levelized compiledcode, switch level functional simulation, synchronous digital systems, Boolean functions, system design, logic design, logic CAD, decision theory, circuit analysis computing, benchmark circuits, branching programs 
15  Amir H. Farrahi, Majid Sarrafzadeh 
System partitioning to maximize sleep time. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
GeoPart, exploitable sleep time, geometric partitioning heuristic, lowpower synthesis, memory refresh circuitry, segment tree data structure, VLSI, logic CAD, integrated circuit design, circuit CAD, circuit optimisation, logic partitioning, partitioning problem, system partitioning 
15  Anmol Mathur, K. C. Chen, C. L. Liu 0001 
Reengineering of timing constrained placements for regular architectures. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems reengineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging 
15  Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe 
A delay model for logic synthesis of continuouslysized networks. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
algebraic factorings, computational simplicity, continuous device sizing, continuouslysized networks, electrical noise, library cell, mapped network, logic design, logic synthesis, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, delay model, power constraints 
15  Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn 
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
acyclic pipelines, areadelay tradeoff, clock skew optimization, cycleborrowing, logic design, combinational circuits, logic CAD, pipeline processing, circuit CAD, circuit optimisation, gate sizing, logic gates, pipelined circuits, timing specifications 
15  Sasan Iman, Massoud Pedram 
Twolevel logic minimization for low power. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
Power Prime Implicants, low power twolevel logic minimization, minimum covering problem, minimum power solution, static CMOS circuits, logic design, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, circuit optimisation, minimisation of switching nets 
15  Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok 
Be careful with don't cares. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
specifications, logic design, logic CAD, correctness, replaceability, don't cares 
15  Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz 
LOT: logic optimization with testabilitynew transformations using recursive learning. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
EXOR gates, logic optimization with testability, multilevel logic circuits, tstfx, logic design, combinational circuits, logic CAD, gate level, randompattern testability, recursive learning 
15  Sudip K. Nag, Rob A. Rutenbar 
Performancedriven simultaneous place and route for islandstyle FPGAs. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
Xilinx 4000series FPGAs, islandstyle FPGAs, performancedriven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout 
15  Sachin S. Sapatnekar, Weitong Chuang 
Power vs. delay in gate sizing: conflicting objectives? 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
powerdelay tradeoffs, shortcircuit power, logic design, logic CAD, integrated circuit design, circuit CAD, optimization problem, circuit optimisation, gate sizing, convex programming, CMOS digital integrated circuits, dynamic power 
15  Irith Pomeranz, Sudhakar M. Reddy 
Functional test generation for delay faults in combinational circuits. 
ICCAD 
1995 
DBLP DOI BibTeX RDF 
gatelevel realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation 
15  Dhruva R. Chakrabarti, Ajai Jain 
An improved hierarchical test generation technique for combinational circuits with repetitive subcircuits. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, highlevel subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph 
15  Hiroaki Ueda, Kozo Kinoshita 
Low power design and its testability. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuckat faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability 
15  Eiji Harada, Janak H. Patel 
Overhead reduction techniques for hierarchical fault simulation. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multilisttraversal method, onepass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI 
15  Shiyi Xu, Gercy P. Dias 
Testability forecasting for sequential circuits. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms 
15  Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck 
Deterministic test generation for nonclassical faults on the gate level. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, librarybased fault modeling strategy, ISCAS benchmark circuits, scanbased circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuckat faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST 
15  Hiroshi Date, Michinobu Nakao, Kazumi Hatayama 
A parallel sequential test generation system DESCARTES based on realvalued logic simulation. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
parallel sequential test generation system, DESCARTES, realvalued logic simulation, redundant fault identification program, algorithmic test generation program, ISCAS '89 benchmark sequential circuits, distributed processing environment oriented system, concurrent accelerative test generation, parallel algorithms, computational complexity, VLSI, fault diagnosis, logic testing, redundancy, design for testability, sequential circuits, logic CAD, VLSI design, stuckat faults, automatic test generation, synchronous sequential circuits, automatic test software, test quality 
15  Wen Ching Wu, ChungLen Lee, Jwu E. Chen 
Identification of robust untestable path delay faults. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, sixvalued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification 
15  Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto 
Universal test complexity of fieldprogrammable gate arrays. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
universal test complexity, arbitrary logic circuits, sequential loading, random access loading, programming schemes, blocksliced loading, configuration memory cells, field programmable gate arrays, fieldprogrammable gate array, computational complexity, fault diagnosis, logic testing, design for testability, fault model, logic CAD, table lookup, lookup tables, automatic test software, Ctestable 
15  Naotake Kamiura, Yutaka Hata, Kazuharu Yamato 
A cellular array designed from a Multiplevalued Decision Diagram and its fault tests. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
multiplevalued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuckat faults 
15  Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita 
Test sequence compaction by reduced scan shift and retiming. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
reduced scan shift, full scan designed circuits, computational complexity, logic testing, transformation, timing, design for testability, sequential circuits, sequential circuit, logic CAD, flipflops, flipflops, retiming, computing time, test length, test sequence generation, test sequence compaction 
15  S. Nandi, Parimal Pal Chaudhuri 
Theory and applications of cellular automata for synthesis of easily testable combinational logic. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuckat faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph 
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