The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for phrase logic design (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1959-1970 (16) 1971-1976 (15) 1977-1979 (19) 1980-1982 (16) 1983-1985 (17) 1986-1987 (15) 1988-1989 (16) 1990-1991 (19) 1992 (15) 1993-1994 (27) 1995 (80) 1996 (24) 1997-1998 (24) 1999 (18) 2000-2001 (26) 2002 (25) 2003 (26) 2004 (23) 2005 (21) 2006 (21) 2007 (27) 2008 (18) 2009 (15) 2010-2011 (25) 2012-2014 (21) 2015-2016 (17) 2017 (17) 2018 (6)
Publication types (Num. hits)
article(195) book(10) incollection(2) inproceedings(400) phdthesis(2)
Venues (Conferences, Journals, ...)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 1605 occurrences of 696 keywords

Results
Found 609 publication records. Showing 609 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
31Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato Multiple-Valued Logic Design Using Multiple-Valued EXOR. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF multiple-valued EXOR, sum operation, multiple valued sum of products expression, binary EXOR of MINs expressions, three valued EXOR of MINs expression, three valued two variable functions, multiple valued EXOR of MINs expressions, MAX of MINs, TSUM of MINs expressions, logic design, neural nets, multivalued logic, logic minimization, minimisation of switching nets, neural computing, multiple valued logic design, multiple-valued logic design
30Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono A Necessary and Sufficient Condition for Lukasiewicz Logic Functions. Search on Bibsonomy ISMVL The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Lukasiewicz logic functions, Lukasiewicz multiple-valued logic, Lukasiewicz implication, logic design, multivalued logic, negation, multiple-valued functions, multiple-valued logic design
27Reiner Hähnle Proof theory of many-valued logic--linear optimization--logic design: connections and interactions. Search on Bibsonomy Soft Comput. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF logic design, mixed integer programming, many-valued logic
27Lech Józwiak Information Relationships and Measures in Application to Logic Design. Search on Bibsonomy ISMVL The full citation details ... 1999 DBLP  DOI  BibTeX  RDF relationships and measures, logic design, information, information modeling, digital systems, functional decomposition
24Samuel C. Lee, Loyd R. Hook IV Logic and Computer Design in Nanospace. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF hypercube, Logic Design, Sequential circuits, nanocomputer
22Kumar N. Lalgudi, Marios C. Papaefthymiou Efficient retiming under a general delay model. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays
22Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu A graph representation for programmable logic arrays to facilitate testing and logic design. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
21Norihiro Fujii, Shûichi Yukita, Nobuhiko Koike, Tosiyasu L. Kunii Top-Down eLearning Tools for Hardware Logic Design. Search on Bibsonomy CW The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
20Susanto Rahardja, Bogdan J. Falkowski Family of Complex Hadamard Transforms: Relationship with Other Transforms and Complex Composite Spectra. Search on Bibsonomy ISMVL The full citation details ... 1997 DBLP  DOI  BibTeX  RDF complex Hadamard transforms, complex composite spectra, binary logic design, complex Hadamard matrices, convolution operation, complex convolution, Boolean functions, codings, Hadamard transforms, multiple-valued logic design
19Yahiko Kambayashi Logic Design of Programmable Logic Arrays. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF two-level circuit, Incompletely specified logic function, reduction of the number of inputs, logic design, programmable logic array, multiple-output function
19Edward J. McCluskey Logic Design of Multivalued I2L Logic Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF switching algebra, multilevel I2L, logic design, multivalued logic, Combinational networks
19Anish Muttreja, Niket Agarwal, Niraj K. Jha CMOS logic design with independent-gate FinFETs. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Paul Pukite, Luke Ludwig Generic discrete event simulations using DEGAS: application to logic design and digital signal processing. Search on Bibsonomy SIGAda The full citation details ... 2007 DBLP  DOI  BibTeX  RDF scheduling, ada, concurrency, discrete-event simulation, logic design, behavioral modeling, design automation, GNAT
19Cheng-Hong Li, Luca P. Carloni Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
18Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka Logic Design Assistence Using Temporal Logic Based Language Tokio. Search on Bibsonomy LP The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
18Vladimir Mateev, Svilena Todorova, Angel Smrikarov Test system in digital logic design virtual laboratory: tasks delivery. Search on Bibsonomy CompSysTech The full citation details ... 2007 DBLP  DOI  BibTeX  RDF digital logic design, knowledge testing system, eLearning, virtual laboratory
17Stephen Y. H. Su IDAS: an integrated design automation system. Search on Bibsonomy AFIPS National Computer Conference The full citation details ... 1984 DBLP  DOI  BibTeX  RDF
17Seokjin Kim, Ramalingam Sridhar A local clocking approach for self-timed datapath designs. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits
17Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward Rational clocking [digital systems design]. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF rational clocking, independently-clocked digital subsystems, finite probability, phase relationship, delays, delays, logic design, logic design, synchronisation, clocks, minimisation of switching nets, digital systems design, synchronization failure
17Eric M. Schwarz, Michael J. Flynn Parallel High-Radix Nonrestoring Division. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF parallel high-radix nonrestoring division, quotient estimation, generalized partial remainder, carry propagate adder, high-radix division, logic design, logic design, latency, computer arithmetic, digital arithmetic, combinatorial algorithm, SRT division
17Jon T. Butler, Kriss A. Schueller On the Equivalence of Cost Functions in the Design of Circuits by Costtable. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF design of circuits by cost-table, least-cost realization, minimal realization, logic design, logic design, equivalence, cost functions
17Shinji Nakamura, Kai-Yu Chu A Single Chip Parallel Multiplier by MOS Technology. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF single chip parallel multiplier, MOS technology, five-counter cell, logic design level, full adder cell design, logic design, integrated logic circuits, multiplying circuits, design optimization, field effect integrated circuits
17Abdullah Y. Al-Zoubi, Sabina Jeschke, Nicole Natho, Jarir Nsour, Olivier Pfeiffer Integration of an online digital logic design lab for it education. Search on Bibsonomy SIGITE Conference The full citation details ... 2008 DBLP  DOI  BibTeX  RDF digital electronics, sequential logic, combinational logic, labview, remote labs, it education
17Kwan Hee Han, Jun Woo Park Development of Object-Oriented Modeling Tool for the Design of Industrial Control Logic. Search on Bibsonomy SERA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16Craig A. Lindley, Mirjam Eladhari Causal Normalization: A Methodology for Coherent Story Logic Design in Computer Role-Playing Games. Search on Bibsonomy Computers and Games The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
16Sushil J. Louis Genetic learning for combinational logic design. Search on Bibsonomy Soft Comput. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Genetic algorithms, Similarity, Case-based-reasoning
15Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas Efficient Reversible Logic Design of BCD Subtractors. Search on Bibsonomy Trans. Computational Science The full citation details ... 2009 DBLP  DOI  BibTeX  RDF BCD subtractors, BCD adders, Reversible logic
15Eric W. Johnson Extensive Introduction to VHDL and PLDs in the Sophomore Year. Search on Bibsonomy MSE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
15Roman L. Lysecky, Frank Vahid A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA fabric, self-improving chips, synthesis, reconfigurable computing, dynamic optimization, system-on-a-chip, platforms, codesign, Hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors
15Hussain Al-Asaad, John P. Hayes Logic Design Validation via Simulation and Automatic Test Pattern Generation. Search on Bibsonomy J. Electronic Testing The full citation details ... 2000 DBLP  DOI  BibTeX  RDF test generation, logic design, fault simulation, error modeling, design validation
15Pramit Chavda, James Jacob, Vishwani D. Agrawal Optimizing Logic Design Using Boolean Transforms. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF multi-level synthesis, Boolean functions, logic design, logic synthesis
15Louise Trevillyan, William H. Joyner Jr., C. Leonard Berman Global Flow Analysis in Automatic Logic Design. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1986 DBLP  DOI  BibTeX  RDF PLA's, Automatic logic design, global flow analysis, compilers, control logic
15Yacoub M. El-Ziq, Stephen Y. H. Su Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1978 DBLP  DOI  BibTeX  RDF diagnosable networks, easily testable networks, field-effect transistors, logic design automation, metal-oxide semiconductor, Boolean functions, logic synthesis, testability, combinational logic, combinational networks, statistical data, computer algorithm
15Vlado Glavinic, Mihael Kukec, Sandi Ljubic Digital Design Mobile Virtual Laboratory Implementation: A Pragmatic Approach. Search on Bibsonomy HCI (5) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF digital logic design, m-devices, touch sensitive screen, m-learning, virtual laboratories
15Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang Charge sharing fault analysis and testing for CMOS domino logic circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
15Pi-Yu Chung, Ibrahim N. Hajj Diagnosis and correction of multiple logic design errors in digital circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
15Takao Saito, Hiroyuki Sugimoto, Masami Yamazaki, Nobuaki Kawato A rule-based logic circuit synthesis system for CMOS gate arrays. Search on Bibsonomy DAC The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
14T. Chan RaceCheck: A Race Logic Audit Program For SoC Designs. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
14G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family. Search on Bibsonomy ISCAS (3) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
14Börje F. Karlsson, Simone Diniz Junqueira Barbosa, Antonio L. Furtado, Marco A. Casanova A Plot-Manipulation Algebra to Support Digital Storytelling. Search on Bibsonomy ICEC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF algebraic formalisms, logic design, storytelling, narratology, plots
13Werner Friesenbichler, Thomas Panhofer, Martin Delvai Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
13Rui Zhang, Pallav Gupta, Lin Zhong 0001, Niraj K. Jha Threshold network synthesis and optimization and its application to nanotechnologies. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
13Samuel C. Lee, Loyd Reed Hook Logic Design of Nano Sequential Machines. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
13Roy M. Proctor A Logic Design Translator Experiment Demonstrating Relationships of Language to Systems and Logic Design. Search on Bibsonomy IEEE Trans. Electronic Computers The full citation details ... 1964 DBLP  DOI  BibTeX  RDF
13Arijit Raychowdhury, Kaushik Roy 0001 A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. Search on Bibsonomy ISMVL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
13Denis V. Popel Conquering Uncertainty in Multiple-Valued Logic Design. Search on Bibsonomy Artif. Intell. Rev. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF machine learning, knowledge representation, information theory, discretization, multiple-valued logic, decision diagrams
13Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj Logic design error diagnosis and correction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
13Kuan Jen Lin, Yi Tang Chiu, Shan Chien Fang Design Optimization and Automation for Secure Cryptographic Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
12Debasis Samanta, Nishant Sinha 0001, Ajit Pal Synthesis of High Performance Low Power Dynamic CMOS Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
12Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima A Component Architecture for FPGA-Based, DSP System Design. Search on Bibsonomy ASAP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
12John D. Lynch, Daniel W. Hammerstrom, Roy Kravitz A Cohesive FPGA-Based System-on-Chip Design Curriculum. Search on Bibsonomy MSE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
12Gin Yee, Carl Sechen Clock-delayed domino for dynamic circuit design. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
12Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud Dual-threshold pass-transistor logic design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dual threshold, pass transistor, low power, leakage
12Jing Huang 0001, Mariam Momenzadeh, Luca Schiano, Marco Ottavi, Fabrizio Lombardi Tile-based QCA design using majority-like logic primitives. Search on Bibsonomy JETC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF processing-by-wire, emerging technologies, QCA
12Sushil J. Louis Learning for Evolutionary Design. Search on Bibsonomy Evolvable Hardware The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
11Kenneth J. Goldman, Paul Gross, Cinda Heeren, Geoffrey L. Herman, Lisa C. Kaczmarczyk, Michael C. Loui, Craig B. Zilles Identifying important and difficult concepts in introductory computing courses using a delphi process: selective compression of unicode arrays in java. Search on Bibsonomy SIGCSE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF discrete math, programming fundamentals, logic design, curriculum, delphi, concept inventory
11Lech Józwiak On the use of term trees for effective and efficient test pattern generation. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF term trees, structural automatic test pattern generation, fault discovery, structural fault model, term tree based ATPG algorithm, nonredundant faults, minimal test set, circuit redundancy, logic design, fault model, data representation, automatic test software
11Tsutomu Sasao, Jon T. Butler Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. Search on Bibsonomy ISMVL The full citation details ... 1997 DBLP  DOI  BibTeX  RDF best sum-of-products expressions, worst sum-of-products expressions, logic design algorithms, product terms, multiple-valued variables, upper bound, switching functions, switching functions, multiple-valued functions
11A. Pal, R. K. Gorai, V. V. S. S. Raju Synthesis of multiplexer network using ratio parameters and mapping onto FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF multiplexing equipment, multiplexer network, ratio parameters, Actel ACT1, MCNC benchmark problems, field programmable gate arrays, FPGAs, VLSI, Boolean functions, Boolean functions, logic design, iterative methods, combinational circuits, combinational circuits, logic CAD, multiplexing, search space, tree network, iterative approach
11Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland Logic design verification via test generation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
11Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
11Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone Charge Sharing Fault Detection for CMOS Domino Logic Circuits. Search on Bibsonomy DFT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit
11Mayukh Bhattacharya, Pinaki Mazumder Noise Margins of Threshold Logic Gates containing Resonant Tunneling Diodes. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Quantum devices, Digital circuits, Resonant Tunneling Diode, Noise margin, Threshold gate
11Lei Xie 0005, Hoang Anh Du Nguyen, Jintao Yu, Ali Kaichouhi, Mottaqiallah Taouil, Mohammad AlFailakawi, Said Hamdioui Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing. Search on Bibsonomy ISVLSI The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
11Robert Wille, Anupam Chattopadhyay, Rolf Drechsler From reversible logic to quantum circuits: Logic design for an emerging technology. Search on Bibsonomy SAMOS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
11Anita Kumari, Sanjukta Bhanja CNT logic knowledge module integrated in digital CMOS logic design course. Search on Bibsonomy MSE The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
11Saket Srivastava, Sanjukta Bhanja Integrating Nano-logic into an Undergraduate Logic Design Course. Search on Bibsonomy MSE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
11Hafiz Md. Hasan Babu, Md. Rafiqul Islam 0001, Amin Ahsan Ali, Mohammad Musa Salehin Akon A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits. Search on Bibsonomy ISMVL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Multi-valued logic (MVL), TMOS logic circuits, Support set, Residual, Literals
11Jukka Lahti, Jorma Kivelä Logic Design and Synthesis with IEEE Logic Symbols in the DEMET System. Search on Bibsonomy VLSI Design The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
11Dominique Snyers, André Thayse From Logic Design to Logic Programming: Theorem Proving Techniques and P-Functions Search on Bibsonomy 1987   DOI  RDF
11Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law, Alexander D. Lopez Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
11Sung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design. Search on Bibsonomy DAC The full citation details ... 1982 DBLP  DOI  BibTeX  RDF
11Yacoub M. El-Ziq, Stephen Y. H. Su Logic design automation of diagnosable MOS combinational logic networks. Search on Bibsonomy DAC The full citation details ... 1977 DBLP  BibTeX  RDF
11D. C. Forslund, Ronald Waxman The Universal Logic Block (ULB) and its Application to Logic Design Search on Bibsonomy SWAT (FOCS) The full citation details ... 1966 DBLP  DOI  BibTeX  RDF
11Daniel H.-Y. Teng, Ronald J. Bolton A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its Applications. Search on Bibsonomy ISMVL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
10A. J. KleinOsowski, David J. Lilja The NanoBox Project: Exploring Fabrics of Self-Correcting Logic Blocks for High Defect Rate Molecular Device Technologies. Search on Bibsonomy ISVLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
10Denis V. Popel, Anita Dani Sierpinski Gaskets for Logic Functions Representation. Search on Bibsonomy ISMVL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Sierpinski gasket, fractal, minimization, logic function, ESOP
10Hong-Yi Huang, Jing-Fu Lin Multiple bulk input differential logic. Search on Bibsonomy APCCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
10Tim Schattkowsky, Marc Lohmann UML Model Mappings for Platform Independent User Interface Design. Search on Bibsonomy MoDELS Satellite Events The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
10Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
10Radomir S. Stankovic Some remarks on terminology in spectral techniques for logic design: Walsh transform and Hadamard matrices. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
10Philip A. Lawson Integrating an Educational Simulation into a Logic Design Course. Search on Bibsonomy ICCAL The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
10Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001 Low-Power and testable circuit synthesis using Shannon decomposition. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
10Vijay Sundaresan, Srividhya Rammohan, Ranga Vemuri Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
10Itai Yarom, Viji Patil Smart-Lint: Improving the Verification Flow. Search on Bibsonomy Haifa Verification Conference The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
10Loyd Reed Hook, Samuel C. Lee The M-Hypercube. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
10Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001 Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
9Eric Keller Building Asynchronous Circuits with JBits. Search on Bibsonomy FPL The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
9Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. Search on Bibsonomy DFT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
9Thelma Estrin The UCLA Brain Research Institute data processing laboratory. Search on Bibsonomy History of Medical Informatics The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
9Andrzej Krasniewski Design for verification testability. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
9Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis. Search on Bibsonomy LP The full citation details ... 1985 DBLP  DOI  BibTeX  RDF
9Haroon Waris, Weiqiang Liu, Pengfei Huang, Ruizhe Ma, Chenghua Wang, Fabrizio Lombardi Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool. Search on Bibsonomy DSL The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
9Zohre Mohammadi-Arfa, Ali Jahanian 0001 DENA: A Configurable Microarchitecture and Design Flow for Biomedical DNA-Based Logic Design. Search on Bibsonomy IEEE Trans. Biomed. Circuits and Systems The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
9Paul Crilly, Grant C. Wyman Using the logic design course as a dress rehearsal for the major design experience. Search on Bibsonomy FIE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
9Mandana Amiri, Andreas G. Veneris, Ivor Ting Design rewiring for power minimization [logic design]. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
9Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty IBM's Blue Logic Design Methodology-Circuits and Physical Design. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
9Haiyan Xu, Takaki Kuroda Design of Database Schemata for Logic Design Education System LODES. Search on Bibsonomy DASFAA The full citation details ... 1989 DBLP  BibTeX  RDF
9Glen G. Langdon Jr. Putting Design into an Introductory Logic Design Course. Search on Bibsonomy IEEE Micro The full citation details ... 1981 DBLP  DOI  BibTeX  RDF
9Bulent I. Dervisoglu Computer aided design techniques applied to logic design. Search on Bibsonomy 1973   RDF
Displaying result #1 - #100 of 609 (100 per page; Change: )
Pages: [1][2][3][4][5][6][7][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license