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Searching for phrase logic synthesis (changed automatically) with no syntactic query expansion in all metadata.

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article(275) book(6) incollection(7) inproceedings(684) phdthesis(7)
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Found 979 publication records. Showing 979 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
61Jason Cong, Kirill Minkovich Optimality Study of Logic Synthesis for LUT-Based FPGAs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
58Reinaldo A. Bergamaschi Bridging the domains of high-level and logic synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
56Jason Cong, Kirill Minkovich Optimality study of logic synthesis for LUT-based FPGAs. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF optimization, logic synthesis, technology mapping, Boolean logic, FPGA lookup table
54Kaushik De, John A. Chandy, Sumit Roy 0003, Steven Parkes, Prithviraj Banerjee Parallel algorithms for logic synthesis using the MIS approach. Search on Bibsonomy IPPS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF combinational logic synthesis, VLSI system design, ProperMIS, portable parallel algorithm, parallel algorithms, parallel algorithms, parallel architectures, logic design, combinational circuits, logic synthesis, logic CAD
52Navin Vemuri, Priyank Kalla, Russell Tessier BDD-based logic synthesis for LUT-based FPGAs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF FPGA, decomposition, logic synthesis, BDD
50Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser Logic optimization by output phase assignment in dynamic logic synthesis. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF dynamic logic synthesis, logic duplication, minimum logic duplication penalty, output phase assignment, logic design, heuristic algorithms, optimal algorithms, domino logic, logic optimization, area overhead, logic functions, inverters
50T. Shinsha, T. Kubo, Y. Sakataya, J. Koshishita, Koichiro Ishihara Incremental logic synthesis through gate logic structure identification. Search on Bibsonomy DAC The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
50José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh Optimization of combinational and sequential logic circuits for low power using precomputation. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle
46Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose Logic synthesis for a single large look-up table. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint
46Mariam Momenzadeh, Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Mark Genoe, Paul Vanoostende, Geert van Wauwe On the use of VHDL-based behavioral synthesis for telecom ASIC design. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
42Geun Rae Cho, Tom Chen Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Mixed PTL/Static, Lower-Power Technology Mapping, Logic Synthesis, Pass Transistor Logic
42Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli Trace driven logic synthesis - application to power minimization. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Low Power, Logic Synthesis
42Martin Lukac, Marek A. Perkowski Projective Measurement-Based Logic Synthesis of Quantum Circuits. Search on Bibsonomy ISMVL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Projective Measurement, Logic Synthesis, Quantum Circuits
41Takahiro Hozumi, Osamu Kakusho, Kazuharu Yamato An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations. Search on Bibsonomy ISMVL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF multilevel circuits, various operations, genetic algorithm, logic synthesis
41Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas Bounding the efforts on congestion optimization for physical synthesis. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF optimization, logic synthesis, physical design, technology mapping, routing congestion
40Unni Narayanan, C. L. Liu 0001 Low power logic synthesis for XOR based circuits. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF vlsi cad logic synthesis, XOR logic, Fixed Polarity Reed Muller Forms, Huffman Algorithm, low power design
40Mark Aagaard, Miriam Leeser Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF weak division, theorem proving, logic synthesis, Software verification, hardware verification
40Kenneth Yan Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
39Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown Delay driven AIG restructuring using slack budget management. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF aig, budget management, logic synthesis, network flow
39TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang Logic synthesis for field-programmable gate arrays. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
38Aleksander Slusarczyk, Lech Józwiak Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
36Chih-Wei Jim Chang, Malgorzata Marek-Sadowska ATPG-based logic synthesis: an overview. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
36Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee A portable parallel algorithm for logic synthesis using transduction. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
36Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli Irredundant sequential machines via optimal logic synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
35Ajay K. Verma, Paolo Ienne Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
35Rui Zhang, Pallav Gupta, Lin Zhong 0001, Niraj K. Jha Threshold network synthesis and optimization and its application to nanotechnologies. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski Quantum logic synthesis by symbolic reachability analysis. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF model checking, formal verification, quantum computing, satisfiability, reversible logic
34Victor Khomenko, Maciej Koutny, Alexandre Yakovlev Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT. Search on Bibsonomy ACSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF net unfoldings, partial order techniques, Petri nets, logic synthesis, asynchronous circuits, SAT, signal transition graphs, STG, self-timed circuits
34Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada Logic synthesis for PLA with 2-input logic elements. Search on Bibsonomy ISCAS (3) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Rui Zhang, Pallav Gupta, Niraj K. Jha Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
33Montek Singh, Steven M. Nowick Synthesis for logical initializability of synchronous finite-state machines. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
32Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF logic synthesis, PLA
32TingTing Hwang, Robert Michael Owens, Mary Jane Irwin Exploiting communication complexity for multilevel logic synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
32TingTing Hwang, Robert Michael Owens, Mary Jane Irwin Multi-Level Logic Synthesis Using Communication Complexity. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
32Sumit Roy 0003, Prithviraj Banerjee A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis. Search on Bibsonomy IPPS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF algebraic factorization, circuit replication, totally independent factorization, L-shaped partitioning strategy, rectangle interaction, ex1010 circuit, sequential kernel extraction algorithms, SIS sequential circuit synthesis system, quality degradation, parallel algorithms, logic synthesis, logic CAD, circuit partitions, divide-and-conquer strategy
31Rui Zhang, Pallav Gupta, Lin Zhong 0001, Niraj K. Jha Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
31Thomas Kutzschebauch, Leon Stok Layout Driven Decomposition with Congestion Consideration. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
31Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
30Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong Protecting Combinational Logic Synthesis Solutions. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
30Dariusz Kania Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition. Search on Bibsonomy EUROMICRO The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
30Jason Cong, Yuzheng Ding Combinational logic synthesis for LUT based field programmable gate arrays. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF FPGA, routing, synthesis, system design, decomposition, technology mapping, simplification, programmable logic, power minimization, logic optimization, delay modeling, delay minimization, computer-aided design of VLSI, area minimization
30Louise Trevillyan An Overview of Logic Synthesis Systems. Search on Bibsonomy DAC The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
30Yexin Zheng, Chao Huang A novel Toffoli network synthesis algorithm for reversible logic. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
30Seapahn Meguerdichian, Miodrag Potkonjak Watermarking while preserving the critical path. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
30Nadine Gergel, Shana Craft, John Lach Modeling QCA for area minimization in logic synthesis. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF CAD, interconnect, logic synthesis, nanotechnology, QCA
30Rupesh S. Shelar, Sachin S. Sapatnekar An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Low Power, Logic Synthesis, Pass Transistor Logic
30Yutaka Hata, Naotake Kamiura, Kazuharu Yamato On Input Permutation Technique for Multiple-Valued Logic Synthesis. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF input permutation technique, multiple-valued logic synthesis, multiple valued sum of products expressions, TSUM, minimal sum of products expressions, permuted logic values, randomly generated functions, input permutation, output permutation, minimization times, window literals, sum of products expressions, set literals, logic design, set theory, multivalued logic
30Chris Sullivan, Alex Wilson, Stephen P. G. Chappell Using C based logic synthesis to bridge the productivity gap. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Mark Aagaard, Miriam Leeser Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification. Search on Bibsonomy CAV The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
30Reinaldo A. Bergamaschi, Andreas Kuehlmann A system for production use of high-level synthesis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
29Rui Zhang, Pallav Gupta, Niraj K. Jha Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Dariusz Kania Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping. Search on Bibsonomy EUROMICRO The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
29Tomasz S. Czajkowski, Stephen Dean Brown Functionally linear decomposition and synthesis of logic circuits for FPGAs. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF decomposition, logic synthesis, linearity, Gaussian elimination
28Robert B. Norwood, Edward J. McCluskey Synthesis-for-scan and scan chain ordering. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
28James Donald, Niraj K. Jha Reversible logic synthesis with Fredkin and Peres gates. Search on Bibsonomy JETC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Quantum computing, reversible logic
28Aijiao Cui, Chip-Hong Chang Stego-signature at logic synthesis level for digital design IP protection. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Vojin G. Oklobdzija An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
28Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
28Balakrishna Kumthekar, Fabio Somenzi Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
28Eugene Goldberg On equivalence checking and logic synthesis of circuits with a common specification. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF common specification, scalable equivalence checking, scalable logic synthesis, toggle equivalence
28Chien-Chung Tsai, Malgorzata Marek-Sadowska Logic Synthesis for Testability. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Fixed-Polarity Reed-Muller Forms, Logic synthesis, Testability
28Daniel Brand, Chandramouli Visweswariah Inaccuracies in power estimation during logic synthesis. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF glitch power, simulation, logic synthesis, power estimation, power optimization
28Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe A delay model for logic synthesis of continuously-sized networks. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF algebraic factorings, computational simplicity, continuous device sizing, continuously-sized networks, electrical noise, library cell, mapped network, logic design, logic synthesis, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, delay model, power constraints
27Unni Narayanan, Peichen Pan, C. L. Liu 0001 Low power logic synthesis under a general delay model. Search on Bibsonomy ISLPED The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
27Ki-Wook Kim, Taewhan Kim, C. L. Liu 0001, Sung-Mo Kang Domino logic synthesis based on implication graph. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
27Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
27Ki-Wook Kim, C. L. Liu 0001, Sung-Mo Kang Implication graph based domino logic synthesis. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
27Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes Signature-Based SER Analysis and Design of Logic Circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
27Tomasz S. Czajkowski, Jonathan Rose A synthesis oriented omniscient manual editor. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF virtex-e, synthesis, manual
27Yun-Yin Lian, Youn-Long Lin Layout-based Logic Decomposition for Timing Optimization. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
27Kaushik De, Chitra Natarajan, Devi Nair, Prithviraj Banerjee RSYN: a system for automated synthesis of reliable multilevel circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
27Wenjing Rao, Alex Orailoglu, Ramesh Karri Topology aware mapping of logic functions onto nanowire-based crossbar architectures. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF logic synthesis, PLA, nanoelectronic, crossbar
27Debesh K. Das, Bhargab B. Bhattacharya Testable design of non-scan sequential circuits using extra logic. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
27Hirendu Vaishnav, Massoud Pedram Logic extraction based on normalized netlengths. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF logic extraction, normalized netlengths, chip area, routing, logic design, logic synthesis, cost function, minimisation of switching nets
26Giovanni De Micheli Synchronous logic synthesis: algorithms for cycle-time minimization. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
26Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje An analysis of the wire-load model uncertainty problem. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
26Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri Application Specific Macro Based Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
26Chih-Yuan Chen, Shing-Wu Tung ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
26Shashidhar Thakur, D. F. Wong Series-parallel functions and FPGA logic module design. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF series-parallel technology mapping, tree-based technology mapping algorithm, universal logic modules, field programmable gate arrays
26Zhaojun Wo, Israel Koren Technology Mapping for Reliability Enhancement in Logic Synthesis. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Mariusz Rawski, Rafal Rzechowski, Zbigniew Jachna, Ireneusz Brzozowski Practical Aspects of Logic Synthesis Based on Functional Decomposition. Search on Bibsonomy DSD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
26Chen-Huan Chiang, Sandeep K. Gupta Random pattern testable logic synthesis. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
26Pranav Ashar, Srinivas Devadas, A. Richard Newton Irredundant interacting sequential machines via optimal logic synthesis. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
26Tomasz S. Czajkowski, Stephen Dean Brown Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Kuo-Hsing Cheng, Shun-Wen Cheng Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF full-swing logic, Low power design, VLSI design, hybrid logic, prime implicant
25Geun Rae Cho, Tom Chen Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Fei Li 0003, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy High-level area and power-up current estimation considering rich cell library. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Fei Li 0003, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy High Level Area and Current Estimation. Search on Bibsonomy PATMOS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
25Tan-Li Chou, Kaushik Roy 0001 Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
24Ellen Sentovich Quick Conservative Causality Analysis. Search on Bibsonomy ISSS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF quick conservative causality analysis, causality problem, standard logic synthesis techniques, combinational circuits, combinational circuit, conservative algorithm
24Angelo P. E. Rosiello, Fabrizio Ferrandi, Davide Pandini, Donatella Sciuto A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Niklas Eén, Alan Mishchenko, Niklas Sörensson Applying Logic Synthesis for Speeding Up SAT. Search on Bibsonomy SAT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Rui Zhang, Niraj K. Jha Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Maitrali Marik, Ajit Pal Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Pawel Kerntopf A new heuristic algorithm for reversible logic synthesis. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF reversible logic circuits, synthesis
24Torsten Mahnke, Walter Stechele, Wolfgang Hoeld Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas Congestion-Aware Logic Synthesis. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
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