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Searching for phrase logic testing (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1970-1988 (22) 1989-1990 (16) 1991-1992 (20) 1993-1994 (23) 1995 (152) 1996 (61) 1997-1998 (17) 1999-2000 (44) 2001-2007 (16) 2008-2018 (13)
Publication types (Num. hits)
article(97) incollection(1) inproceedings(285) phdthesis(1)
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The graphs summarize 2963 occurrences of 706 keywords

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Found 384 publication records. Showing 384 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
33Arabi Keshk, Yukiya Miura, Kozo Kinoshita Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
29Teruhiko Yamada, Tsuyoshi Sasaki On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF 4JL gate, Josephson logic circuit, current testing, defect coverage
28Mehdi Baradaran Tahoori Application-Dependent Testing of FPGAs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Rubin A. Parekhji Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
20Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick, Donald L. Wheater Low-Cost Testing of High-Density Logic Components. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
20Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang Novel techniques for improving testability analysis. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF closed-form formulation, implication reasoning, TAIR, tree-structured circuit, logic testing, logic testing, controllability, controllability, built-in self test, automatic test pattern generation, BIST, observability, observability, stuck-at fault, shift registers, testability analysis, test patterns
20Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen Peak-power reduction for multiple-scan circuits during test application. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
20Mukund Sivaraman, Andrzej J. Strojwas Diagnosis of parametric path delay faults. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF parametric path delay faults, chip failure, fabrication process parameter values, path sensitization mechanism, path delay conditions, ISCAS'89 benchmark circuits, path segment, circuit failure, fault diagnosis, logic testing, logic testing, delays, probability, probability, statistical analysis, statistical analysis, integrated circuit testing, failure analysis, diagnosability, delay fault testing, IC testing, production testing
20Nur A. Touba, Edward J. McCluskey Test point insertion based on path tracing. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF probabilistic techniques, primary inputs, insertion methods, VLSI, VLSI, fault diagnosis, logic testing, logic testing, probability, built-in self test, timing, integrated circuit testing, BIST, automatic testing, fault coverage, test point insertion, path tracing, circuit-under-test
20Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges Statistical estimation of delay fault detectabilities and fault grading. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation
20Shiyi Xu, Gercy P. Dias Testability forecasting for sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms
20Shih-Yuang Su, Cheng-Wen Wu Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF sequential faults, ILA, M-testability, constant-length test sequence, pipelined array multiplier, sequential fault testing, logic testing, logic testing, sequential circuits, test pattern generation, logic arrays, combinatorial circuits, test vectors, C-testability, iterative logic arrays, iterative logic array
19Noritaka Kobayashi, Tatsuhiro Tsuchiya, Tohru Kikuno Applicability of Non-Specification-Based Approaches to Logic Testing for Software. Search on Bibsonomy DSN The full citation details ... 2001 DBLP  DOI  BibTeX  RDF factor covering design, software testing, logic testing, mutation analysis, boolean specification
19Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada Test Time Reduction for I DDQ Testing by Arranging Test Vectors. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
17Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
16Joan Figueras, Michel Renovell Current testing in dynamic CMOS circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF dynamic CMOS, test technique, integrated circuit, Current testing
15Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates. Search on Bibsonomy Asian Test Symposium The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
13Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi Using the inter- and intra-switch regularity in NoC switch testing. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
13Wei-Kang Huang, Fred J. Meyer, Xiao-Tao Chen, Fabrizio Lombardi Testing configurable LUT-based FPGA's. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
10Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia MERO: A Statistical Approach for Hardware Trojan Detection. Search on Bibsonomy CHES The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
10Stephen Pateras Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
10Jason G. Brown, R. D. (Shawn) Blanton A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. Search on Bibsonomy J. Electronic Testing The full citation details ... 2007 DBLP  DOI  BibTeX  RDF fault diagnostic accuracy, nanofabrication, regular architectures, nanoFabric, fault diagnosis, logic testing, reconfigurability, integrated circuit testing, fault coverage, nanoelectronics, high defect densities
10Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. Search on Bibsonomy J. Electronic Testing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF scan tree, logic testing, design for testability, sequential circuit
10Antonio Zenteno, Víctor H. Champac, Joan Figueras Detectability Conditions of Full Opens in the Interconnections. Search on Bibsonomy J. Electronic Testing The full citation details ... 2001 DBLP  DOI  BibTeX  RDF logic testing, IDDQ testing, opens, defect modeling
10Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. Search on Bibsonomy PRDC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
10Masayuki Tsukisaka, Takashi Nanya A testable design for asynchronous fine-grain pipeline circuits. Search on Bibsonomy PRDC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
10Irith Pomeranz, Sudhakar M. Reddy Fault diagnosis based on parameters of output responses. Search on Bibsonomy PRDC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF output responses parameters, unmodeled faults, fault diagnosis, fault diagnosis, logic testing, sequential circuits, dictionaries, synchronous sequential circuits, diagnostic resolution
10Irith Pomeranz, Sudhakar M. Reddy Reducing test application time for full scan circuits by the addition of transfer sequences. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits
10Michael J. Liebelt, Cheng-Chew Lim A method for determining whether asynchronous circuits are self-checking. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
10Chen-Huan Chiang, Sandeep K. Gupta BIST TPG for SRAM cluster interconnect testing at board level. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
10Paul Chang, Brion L. Keller, Sarala Paliwal Effective parallel processing techniques for the generation of test data for a logic built-in self test system. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
10Ameet Bagwe, Rubin A. Parekhji Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
10Ming-Der Shieh, Hsin-Fu Lo, Ming-Hwa Sheu High-speed generation of LFSR signatures. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF high-speed generation, LFSR signatures, compaction simulation, single-input signature register, equivalent multiple-input implementation, finite field theory, high-speed signature computations, lookahead technique, internal-XOR LFSR, external-XOR LFSR, performance evaluation, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, BIST, linear feedback shift register, binary sequences, subsequences
10Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda High speed IDDQ test and its testability for process variation. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing
10Eric MacDonald, Nur A. Touba Testing domino circuits in SOI technology. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits
10Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou etection of SRAM cell stability by lowering array supply voltage. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron
10Hsin-Po Wang, Jon Turino DFT and BIST techniques for the future. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF multimillion gate system-on-chip, multinational design, logic testing, built-in self test, design for testability, quality, BIST, economics, DFT, integrated circuit design, time to market, production testing, IC design, integrated circuit economics
10Wei-Lun Wang, Kuen-Jong Lee Accelerated test pattern generators for mixed-mode BIST environments. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
10Ruofan Xu, Michael S. Hsiao Embedded core testing using genetic algorithms. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF gate level implementation, user defined logic, random inputs, high level benchmarks, wrapper size, genetic algorithms, genetic algorithms, fault diagnosis, logic testing, controllability, controllability, high level synthesis, automatic test pattern generation, observability, observability, application specific integrated circuits, fault coverage, SOC, test application time, test patterns, embedded core testing, internal state
10Marie-Lise Flottes, Christian Landrault, A. Petitqueux Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
10Ismet Bayraktaroglu, Alex Orailoglu Accumulation-based concurrent fault detection for linear digital state variable systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF concurrent fault detection, linear digital state variable systems, algorithmic fault detection scheme, accumulation-based approach, fault diagnosis, logic testing, error detection, error detection, linear systems, digital filters, digital signal processing chips, digital systems, area overhead
10Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy Enhanced untestable path analysis using edge graphs. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF untestable path analysis, edge graphs, partial path sensitization, edge graph, logic testing, logic circuits, logic circuits, path delay fault testing
10Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
10Toshiyuki Maeda, Kozo Kinoshita Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
10Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy Fsimac: a fault simulator for asynchronous sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
10Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita Test sequence compaction for sequential circuits with reset states. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
10Wu-Tung Cheng Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
10Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer A new framework for static timing analysis, incremental timing refinement, and timing simulation. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation
10Hiromi Hiraishi Verification of deadlock free property of high level robot control. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF deadlock free property, high level robot control, verification algorithm, task control architecture, concurrent robot control processes, symbolic model verifier, symbolic model checking algorithm, robots, formal verification, logic testing, concurrency control, message passing, symbol manipulation, safety properties, liveness properties
10Shiyi Xu, Wei Cen Forecasting the efficiency of test generation algorithms for digital circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
10Der-Cheng Huang, Wen-Ben Jone An efficient parallel transparent diagnostic BIST. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF parallel transparent diagnostic BIST, built-in self-diagnosis method, multiple embedded memory arrays, transparent diagnostic interface, redundant read/write/shift operations, march algorithm, TDiagRSMarch algorithm, low hardware overhead, test time reduction, diagnostic efficiency, parallel algorithms, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic testing, test coverage, integrated memory circuits
10Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara Single-control testability of RTL data paths for BIST. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF single-control testability, RTL data paths, BIST method, response analyzers, DFT method, high fault coverage, low hardware overhead, VLSI, logic testing, built-in self test, integrated circuit testing, design for testability, automatic test pattern generation, ATPG, test pattern generators, delay faults, VLSI circuits, at-speed testing, transition faults, digital integrated circuits, single stuck-at faults, hierarchical test
10Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch An adjacency-based test pattern generator for low power BIST design. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
10Michiko Inoue, Emil Gizdarski, Hideo Fujiwara A class of sequential circuits with combinational test generation complexity under single-fault assumption. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
10Valentin Muresan, Xiaojun Wang 0001, Valentina Muresan, Mircea Vladutiu Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF distribution-graph based approach, extended tree growing technique, power-constrained block-test scheduling, unequal-length block-test scheduling, power dissipation constraints, test concurrency, assigned power dissipation limits, balanced test power dissipation, least mean square error function, global priority function, system-level test scheduling algorithm, scheduling, VLSI, fault diagnosis, logic testing, high level synthesis, integrated circuit testing, automatic test pattern generation, trees (mathematics), least mean squares methods
10Irith Pomeranz, Sudhakar M. Reddy On the feasibility of fault simulation using partial circuit descriptions. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF partial circuit description, gate-level circuits, subcircuits, logic testing, fault simulation, fault simulation, memory requirements
10F. Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu DFT closure. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF area requirement, power requirement, timing closure flow, logic testing, SoC, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, ASIC, testability
10Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang Charge sharing fault analysis and testing for CMOS domino logic circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
10Yiorgos Makris, Jamison Collins, Alex Orailoglu Fast hierarchical test path construction for DFT-free controller-datapath circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fast hierarchical test path construction, DFT-free controller-datapath circuits, transparency based scheme, locally generated vectors, global design test, influence tables, valid control state sequences, module testing, fault coverage levels, vector counts, logic testing, test generation, automatic test pattern generation, ATPG, computational cost reduction
10Andrzej Hlawiczka, Michal Kopec Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF serial seeding, linear hybrid cellular automata, n-cell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, n-bit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flip-flops, flip-flops, shift registers, pattern generators, integrated circuit economics
10Junichi Hirase, Shinichi Yoshimura Faster processing for microprocessor functional ATPG. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF microprocessor functional ATPG, fault coverage improvement, short test pattern, processing speed increase, logic testing, integrated circuit testing, automatic test pattern generation, identification, test pattern generation, functional testing, microprocessor chips, instruction sets, instruction sets, microprocessor tests
10Emil Gizdarski, Hideo Fujiwara Spirit: satisfiability problem implementation for redundancy identification and test generation. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets
10Jin-Cherng Lin, Pu-Lin Yeh Using genetic algorithms for test case generation in path testing. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF survival of the fittest theory, operator sequences, genetic algorithms, genetic algorithms, real-time systems, logic testing, SIMILARITY, automatic test pattern generation, test case generation, fitness function, program execution, path testing
10Wen-Feng Chang, Cheng-Wen Wu Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Fault tolerance, logic testing, on-line testing, totally-self-checking checker, m-out-of-n code
10Michael L. Bushnell, John Giraldi A Functional Decomposition Method for Redundancy Identification and Test Generation. Search on Bibsonomy J. Electronic Testing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF redundancy identification, logic testing, automatic test generation, backtracing
10Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF simulation-based test generation, distributed memory MIMD machines, shared memory MIMD machines, parallel search strategies, logic testing, fault coverage, NP-complete problems, VLSI circuits, parallel genetic algorithms, sequential circuit test generation
10Richard M. Chou, Kewal K. Saluja Sequential Circuit Testing: From DFT to SFT. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques
10Zdenek Kotásek, F. Zboril RT level testability analysis to reduce test application time. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF register transfer level testability analysis, RTL element classification, RTL circuit transformation, labelled directed graph, PROLOG environment, implementation principles, logic testing, test application time reduction
10David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi Testing of programmable logic devices (PLD) with faulty resources. Search on Bibsonomy DFT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices
10Rolf Drechsler, Martin Keim, Bernd Becker 0001 Fault Simulation in Sequential Multi-Valued Logic Networks. Search on Bibsonomy ISMVL The full citation details ... 1997 DBLP  DOI  BibTeX  RDF sequential multi-valued logic networks, multi-valued logic networks, logic testing, sequential circuits, fault models, fault simulator, random pattern testability
10Irith Pomeranz, Sudhakar M. Reddy EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF EXTEST, test generation procedure, logic testing, fault coverage, synchronous sequential circuits, test sequences
10Kaushik De Test methodology for embedded cores which protects intellectual property. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology
10Irith Pomeranz, Sudhakar M. Reddy On n-detection test sequences for synchronous sequential circuits343. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF n-detection test sequences, stuck-at fault detection, test generation procedures, logic testing, fault simulation, synchronous sequential circuits, defect coverages
10Christos A. Papachristou, Mikhail Baklashov A test synthesis technique using redundant register transfers. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF behavioral variables, conditional statements, redundant register transfers, structural signals, test synthesis technique, testability metrics, graph theory, logic testing, controllability, high level synthesis, VHDL, observability, fault coverage, data path, hardware overhead, behavioral descriptions
10Dominik Stoffel, Wolfgang Kunz Record & play: a structural fixed point iteration for sequential circuit verification. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design
10Tzuhao Chen, Ibrahim N. Hajj GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF GOLDENGATE, digital VLSI circuits, electrical-level simulation, event-driven technique, logic/I/sub DDQ/ testing, logic testing, sequential circuits, combinational circuits, bridging fault simulator
10Vishwani D. Agrawal, David Lee Characteristic polynomial method for verification and test of combinational circuits. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF combinational circuit test, randomly selected integers, input variables, integer-valued transform functions, fixed domain, multiple samples, randomly selected real numbers, output logic, logic testing, probability, Boolean functions, Boolean functions, combinational circuits, polynomials, error probability, characteristic polynomial
10Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal Parallel concurrent path-delay fault simulation using single-input change patterns. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF concurrent path-delay fault simulation, single-input change patterns, singly-testable path-delay faults, random values, rising transitions, falling transitions, sixteen-valued algebra, machine word parallelism, ISCAS '85 benchmarks, ISCAS '89 benchmarks, parallel algorithms, fault diagnosis, logic testing, delays, Boolean functions, sequential circuits, logic CAD, circuit analysis computing, flip-flops, Boolean operations
10S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF programmable cellular automata, polynomial algebraic tools, faulty signatures, multiple attractor, fault dictionary size, cascadable structure, VLSI, fault diagnosis, fault diagnosis, logic testing, partitions, cellular automata, integrated circuit testing, automatic testing, VLSI circuits, logic partitioning, signature analyzer
10Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas Statistical path delay fault coverage estimation for synchronous sequential circuits. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
10Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal On test coverage of path delay faults. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF two-pass test generation method, falling transition, line delay test, longest sensitizable path, decreasing length, redundant stuck-at fault, computational complexity, fault diagnosis, logic testing, delays, redundancy, combinational circuits, fault simulation, circuit analysis computing, test coverage, path delay faults, benchmark circuits, coverage metric, combinational logic circuits, longest paths
10Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal Improving accuracy in path delay fault coverage estimation. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fault coverage estimation, simulated vector pair, exact fault simulation, fixed-length path-segments, fan-in branches, fan-out branches, flagged path-segments, segment lengths, combinational paths, graph theory, fault diagnosis, logic testing, delays, combinational circuits, logic CAD, circuit analysis computing, path delay fault, approximate methods, CPU time
10Tapan J. Chakraborty, Vishwani D. Agrawal Design for high-speed testability of stuck-at faults. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF design for high-speed testability, stuck-at fault detection, signal transition, timing hazard, multivalue algebra, dh-robust test, sequential feedback, reconvergent fanout, cycle-free sequential circuit, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, partial scan, test generation algorithm, critical path delay
10Debesh Kumar Das, Bhargab B. Bhattacharya Does retiming affect redundancy in sequential circuits? Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF combinational redundancy, sequential redundancy, fault diagnosis, logic testing, timing, redundancy, test generation, design for testability, sequential circuits, sequential circuit, fault, retiming, logic optimization, operation speed
10Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak Syndrome signature in output compaction for VLSI BIST. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
10Ghassan Al Hayek, Yves Le Traon, Chantal Robach Considering Test Economics in the Process of Hardware/Software Partitioning. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF hardware/software testing, specifications, logic testing, estimate, testability, co-design, mutation-test, hardware/software partitioning, test economics
10Mou Hu Design of One-Vector Testable Binary Systems Based on Ternary Logic. Search on Bibsonomy ISMVL The full citation details ... 1996 DBLP  DOI  BibTeX  RDF ternary circuits, MOS circuit, logic testing, built-in self-test, design for testability, multiple-valued logic
10Rolf Drechsler Verification of Multi-Valued Logic Networks. Search on Bibsonomy ISMVL The full citation details ... 1996 DBLP  DOI  BibTeX  RDF multi-valued logic networks verification, ordered multi-valued decision diagrams, two-valued circuits, formal verification, heuristics, logic testing, directed graphs, directed acyclic graph, multivalued logic circuits, functional equivalence
10R. D. (Shawn) Blanton, John P. Hayes Design of a fast, easily testable ALU. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit
10Wei-Kang Huang, Fabrizio Lombardi An approach for testing programmable/configurable field programmable gate arrays. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model
10Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel Automatic test generation using genetically-engineered distinguishing sequences. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF two-phase algorithm, fault effects, DIGATE, genetic algorithms, genetic algorithm, fault diagnosis, logic testing, sequential circuits, sequential circuit, automatic testing, sequences, flip-flops, automatic test generation, distinguishing sequence
10Peter Wohl, John A. Waicukauski, Matthew Graf Testing "untestable" faults in three-state circuits. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF three-state circuits, complex CMOS designs, nonconventional circuits, test generation techniques, circuit particularities, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, test coverage, multivalued logic circuits, computer testing, CPU time, test vector generation, untestable faults, automatic learning
10Masaru Sanada A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF CAD-based failure diagnosis technology, CMOS LSI, abnormal Iddq phenomenon, physical damage detection, faulty blocks, failure point localization, Iddq test patterns, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, circuit CAD, large scale integration
10Jalal A. Wehbeh, Daniel G. Saab Initialization of sequential circuits and its application to ATPG. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF initialization sequence, X-value simulation, functional initializability, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, ATPG, automatic testing, integrated logic circuits, structural decomposition
10Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz On minimizing the number of test points needed to achieve complete robust path delay fault testability. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF robust path delay fault testability, RD fault identification, fault diagnosis, logic testing, delays, test generation, combinational circuits, combinational circuit, test point insertion
10Nur A. Touba, Edward J. McCluskey Applying two-pattern tests using scan-mapping. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests
10Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis An asynchronous totally self-checking two-rail code error indicator. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF asynchronous TSC error indicator, totally self-checking error indicator, concurrent detection, two-rail code error indicator, CMOS implementation, VLSI, logic testing, delays, integrated circuit testing, error detection, automatic testing, asynchronous circuits, CMOS logic circuits, delay faults
10John W. Sheppard, William R. Simpson Improving the accuracy of diagnostics provided by fault dictionaries. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF diagnostics accuracy improvement, digital circuit diagnosis, information flow model, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, circuit analysis computing, digital integrated circuits, fault dictionaries, nearest neighbor classification
10Krishna B. Rajan, David E. Long, Miron Abramovici Increasing testability by clock transformation (getting rid of those darn states). Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF clock transformation, sequential test generation, darn states, easy-to-reach states, logic testing, partitioning, design for testability, sequential circuits, DFT, fault coverage, testability, flip-flops, flip-flops, clocks, logic partitioning
10Michel Renovell, P. Huc, Yves Bertrand Bridging fault coverage improvement by power supply control. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF bridging fault coverage, power supply control, resistance interval, faulty value, VLSI, VLSI, fault diagnosis, logic testing, integrated circuit testing, automatic testing, logic circuits, parametric model, benchmark circuits
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