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Publication years (Num. hits)
1993-1995 (55) 1996-1997 (29) 1998-1999 (36) 2000 (19) 2001 (20) 2002 (37) 2003 (57) 2004 (56) 2005 (61) 2006 (67) 2007 (67) 2008 (42) 2009 (44) 2010 (29) 2011-2012 (22) 2013-2014 (27) 2015-2016 (19) 2017-2018 (13)
Publication types (Num. hits)
article(157) book(5) incollection(1) inproceedings(535) phdthesis(1) proceedings(1)
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Found 700 publication records. Showing 700 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
52Kanishka Lahiri, Anand Raghunathan Power analysis of system-level on-chip communication architectures. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
43Soheil Modirzadeh, Brian Fuller, Sandeep Mirchandani, Jon McDonald, Ran Avinun, Camille Kokozaki It is all about power analysis, exploration and trade-offs. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF IDT, NXP, broadcom, cadence, system design and verification, technical panel, low power, low power design
43Subhomoy Chattopadhyay Low power design techniques for nanometer design processes: 65 nm and smaller. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF 65 nm, low power, embedded design
37Swarup Bhunia, Kaushik Roy 0001 Low power design under parameter variations. Search on Bibsonomy SoCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Ying-Wen Bai, Chun-Yang Tsai Design and implementation of a low-power workstation. Search on Bibsonomy CCECE The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
33Andrea Bona, Vittorio Zaccaria, Roberto Zafalon Low Effort, High Accuracy Network-on-Chip Power Macro Modeling. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Network-on-Chip power analysis, communication based low power design, system-level energy optimization
33Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen Design theory and implementation for low-power segmented bus systems. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF OLA tree, bus graph model, bus segmentation, bus segmentation cell, low-power design flow, low-power design, ASIC design
32E. Seebacher, Gerhard Rappitsch, H. Höller Process Characterization for Low VTH and Low Power Design. Search on Bibsonomy PATMOS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Kevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, Derek Chiou Low-Power Design and Temperature Management. Search on Bibsonomy IEEE Micro The full citation details ... 2007 DBLP  DOI  BibTeX  RDF low-power design, power management, hardware, energy-aware systems, temperature-aware design
32Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske Low Power Design of FSMs by State Assignment and Disabling Self-Loops. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF FSM synthesis, encoding constraints, low power design, clock gating, state assignment
31Shih-Hsu Huang An effective low power design methodology based on interconnect prediction. Search on Bibsonomy SLIP The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
30Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi ILP models for simultaneous energy and transient power minimization during behavioral synthesis. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
29Mohamed Abbas, Makoto Ikeda, Kunihiro Asada Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime. Search on Bibsonomy DFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
28An-Yeu Wu, K. J. Ray Liu Algorithm-based low-power transform coding architectures: the multirate approach. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
28Martin Feldhofer, Sandra Dominikus, Johannes Wolkerstorfer Strong Authentication for RFID Systems Using the AES Algorithm. Search on Bibsonomy CHES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF symmetric challenge-response, Radio frequency identification (RFID), low-power design, Advanced Encryption Standard (AES)
27Min Ni, Seda Ogrenci Memik Thermal-induced leakage power optimization by redundant resource allocation. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Zhijun Huang, Milos D. Ercegovac High-Performance Low-Power Left-to-Right Array Multiplier Design. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design
27Sung-Bae Park DLV (Deep Low Voltage): Circuits and Devices. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Tarun Sairam, Wei Zhao, Yu Cao Optimizing finfet technology for high-speed and low-power design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power, energy, variations, speed, threshold voltage, FinFET, noise margin
26Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez Dynamic Power Management for Microprocessors: A Case Study. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
26Kaijian Shi, David Howard Challenges in sleep transistor design and implementation in low-power designs. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF methodology, low-power design, power gating, sleep transistor
26Michael Eisenring, Jürgen Teich Interfacing Hardware and Software. Search on Bibsonomy FPL The full citation details ... 1998 DBLP  DOI  BibTeX  RDF automatic interface synthesis, low power design, rapid prototyping, hardware/software codesign
26Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi Simultaneous peak and average power minimization during datapath scheduling for DSP processors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages
25Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich The opportunity cost of low power design: a case study in circuit tuning. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low power design, productivity, circuit tuning
25Reza Lotfi, Mohammad Taherzadeh-Sani, M. Yaser Azizi, Omid Shoaei A low-power design methodology for high-resolution pipelined analog-to-digital converters. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low-power design, operational amplifiers, pipelined analog-to-digital converters
25Vishwani D. Agrawal Low-Power Design by Hazard Filtering. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF hazard filtering, multiple transitions, hazard pulses, differential delay, low-power design, power consumption, CMOS logic circuits, CMOS circuit, logic gate, gate delays
25Hiroaki Ueda, Kozo Kinoshita Low power design and its testability. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability
25Mircea R. Stan, Wayne P. Burleson Bus-invert coding for low-power I/O. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
25Enrico Macii, Massoud Pedram, Dirk Friebel, Robert C. Aitken, Antun Domic, Roberto Zafalon Low-power design tools: are EDA vendors taking this matter seriously? Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25James Ayers, Kartikeya Mayaram, Terri S. Fiez Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Shi-Hao Chen, Jiing-Yuan Lin Experiences of low power design implementation and verification. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Naehyuck Chang In-House Tools for Low-Power Embedded Systems. Search on Bibsonomy ICESS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Allan Crone, Gabriel Chidolue Functional Verification of Low Power Designs at RTL. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Low power aware management, Corruption, UPF, Simulation, Retention, PCF
24Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Abdoul Rjoub, M. Alrousan, O. Jarrah, Odysseas G. Koufopavlou Multi-level low swing voltage values for low power design applications. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
24Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang Low power design of H.264 CAVLC decoder. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Brian A. White, Mohamed I. Elmasry Low-power design of decimation filters for a digital IF receiver. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
24Andrew Wolfe A case study in low-power system-level design. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF low-power system-level design, touchscreen interface device, RS232 communication lines, design automation community, real-time systems, logic design, systems analysis, personal computer, low-power embedded system
24Mark S. Bright, Tughrul Arslan Multi-objective design strategy for high-level low power design of DSP systems. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
24Jan M. Rabaey, Dennis Sylvester, David T. Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang Reshaping EDA for power. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24Jan M. Rabaey Traveling the Wild Frontier of Ultra Low-Power Design. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
23Jerry Frenkil Tools and Methodologies for Low Power Design. Search on Bibsonomy DAC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
23Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram Charge recycling in MTCMOS circuits: concept and analysis. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF low power design, MTCMOS, charge recycling
23Sangwoon Yang, Jinsub Park, Younggap You The Smallest ARIA Module with 16-Bit Architecture. Search on Bibsonomy ICISC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Cryptography, Low Power Design, ARIA
23Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Liang-Gee Chen Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF parallel processing, motion estimation, H.264, data reuse
23Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001 Case Study of Reliability-Aware and Low-Power Design. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
23Nathaniel J. August, Dong Sam Ha Low power design of DCT and IDCT for low bit rate video codecs. Search on Bibsonomy IEEE Trans. Multimedia The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22Paul Flugger RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches. Search on Bibsonomy PATMOS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
22Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001 CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Mandeep Singh, Christophe Giacomotto, Bart R. Zeydel, Vojin G. Oklobdzija Logic Style Comparison for Ultra Low Power Operation in 65nm Technology. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
22Sung-Mo Kang Elements of low power design for integrated systems. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low power integrated circuits, VLSI, CMOS
21Yong Li 0006, Zhiying Wang, Kui Dai A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units. Search on Bibsonomy CIT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
21R. Shalem, Lizy Kurian John, Eugene John A Novel Low Power Energy Recovery Full Adder Cell. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
21Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
21Zhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta 0001 A gateway node with duty-cycled radio and processing subsystems for wireless sensor networks. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Embedded systems, power savings, gateway, sensor nodes
21Deming Chen, Jason Cong, Yiping Fan Low-power high-level synthesis for FPGA architectures. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF FPGA power reduction, RT-level power estimation, data path optimization
21Chih-Wen Hsueh, Jen-Feng Chung, Lan-Da Van, Chin-Teng Lin Anticipatory access pipeline design for phased cache. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
21Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell Variable Input Delay CMOS Logic for Low Power Design. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
21Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis Early Power-Aware Design & Validation: Myth or Reality? Search on Bibsonomy DAC The full citation details ... 2007 DBLP  BibTeX  RDF
21Kaushal R. Gandhi, Nihar R. Mahapatra Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF operand encoding, opera- tion bypass, low-power design, soft error
21Sung I. Park, Vijay Raghunathan, Mani B. Srivastava Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systems. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low power design, dynamic power management, embedded system design, energy efficient design
20Anantha Chandrakasan Ultra low power digital signal processing. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
20Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. Search on Bibsonomy ISVLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
20Chia-Ping Lin, Po-Chih Tseng, Liang-Gee Chen Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications. Search on Bibsonomy ICME The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
20Chen-Yuan Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng, Wu-Shiung Feng A 24GHz low-power CMOS receiver design. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
19Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi Discrete-time battery models for system-level low-power design. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
19Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
19Naehyuck Chang, Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Hyung Gyu Lee, Hojun Shim Graduate Class for System-Level Low-Power Design. Search on Bibsonomy MSE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19M. R. Nabavi A 1-V 12-bit switched-op amp pipelined ADC with power optimization. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
18Kimiyoshi Usami, Mark Horowitz Clustered voltage scaling technique for low-power design. Search on Bibsonomy ISLPD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
18Ravi Surepeddi System Verilog for Quality of Results (QoR). Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF System Verilog Design Quality Results
17Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
17Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici Scan Architecture for Shift and Capture Cycle Power Reduction. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
17Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen Low power and power aware fractional motion estimation of H.264/AVC for mobile applications. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
17Zhiyong He, Sébastien Roy 0002, Paul Fortier High-speed and low-power design of parallel turbo decoder. Search on Bibsonomy ISCAS (6) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
17Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
17George Sobral Silveira, Alisson Vasconcelos De Brito, Elmar U. K. Melcher Functional verification of power gate design in SystemC RTL. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF simulation, SystemC, RTL, functional verification, power gate
17Vyas Krishnan, Srinivas Katkoori Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
17Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001 A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
17Xin Zhao, Yici Cai, Qiang Zhou 0001, Xianlong Hong A novel low-power physical design methodology for MTCMOS. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
16Kimiyoshi Usami Overview on Low Power SoC Design Technology. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16Suman Kalyan Mandal, Rabi N. Mahapatra, Praveen Bhojwani, Saraju P. Mohanty IntellBatt: Toward a Smarter Battery. Search on Bibsonomy IEEE Computer The full citation details ... 2010 DBLP  DOI  BibTeX  RDF IntellBatt, Battery management, Smart battery, Low-power design, Hardware
16Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, Weiwu Hu Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF FMA, dual-path FMA, low-power design
16Jason Helge Anderson, Chirag Ravishankar FPGA power reduction by guarded evaluation. Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
16Chacko John Deepu, Xiaoyuan Xu, Xiaodan Zou, Libin Yao, Yong Lian An ECG-on-Chip for Wearable Cardiac Monitoring Devices. Search on Bibsonomy DELTA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF QRS detection, ECG-on-Chip, Low Power design, Wearable devices, Electrocardiography
16Vincent C. Gaudet, Warren J. Gross Switching Activity in Stochastic Decoders. Search on Bibsonomy ISMVL The full citation details ... 2010 DBLP  DOI  BibTeX  RDF stochastic decoding, low-power design, iterative decoding, LDPC
16Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF WSN node, hardware specialization, microcoded architecture, low-power design
16John B. Goodenough, Rob Aitken Post-silicon is too late avoiding the $50 million paperweight starts with validated designs. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF low power design, emulation, post-silicon validation
16Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy 0001, Srimat T. Chakradhar Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF scalable effort, support vector machines, low power design, recognition, mining, approximate computing
16Weixun Wang, Xiaoke Qin, Prabhat Mishra Temperature- and energy-constrained scheduling in multitasking systems: a model checking approach. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF dvs, temperature-aware, model checking, low power design
16Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija Energy efficient implementation of parallel CMOS multipliers with improved compressors. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF arithmetic and logic structures, VLSI, low-power design, high- speed arithmetic, booth encoding
16Felipe Klein, Alexandro Baldassin, João Moreira, Paulo Centoducatte, Sandro Rigo, Rodolfo Azevedo STM versus lock-based systems: an energy consumption perspective. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF lock-based systems, parallel programming, low power design, transactional memory, multi-core
16Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella, Antonio González 0001, Oguz Ergin Exploring the limits of early register release: Exploiting compiler analysis. Search on Bibsonomy TACO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF compiler, energy efficiency, Low-power design, microarchitecture, register file
16Choong Jin Hyun, Myung Hoon Sunwoo Low Power Complexity-Reduced ME and Interpolation Algorithms for H.264/AVC. Search on Bibsonomy Signal Processing Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Motion estimation, Low power design, H.264/AVC, Motion compensation, Data reuse
16Daler N. Rakhmatov Battery voltage modeling for portable systems. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF accuracy-complexity tradeoff, battery performance, battery-powered systems, Low-power design, analytical modeling
16Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low-power design, process variations, leakage current, Body biasing
16Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Hoi-Jun Yoo A Low-Power Multimedia SoC with Fully Programmable 3D Graphics for Mobile Devices. Search on Bibsonomy IEEE Computer Graphics and Applications The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Mobile multimedia SoC, mobile unified shader, low-power design, 3D graphics, programmable
16P. T. V. Bhuvaneswari, R. Balakumar, Vijay Vaidehi, P. Balamuralidhar Solar Energy Harvesting for Wireless Sensor Networks. Search on Bibsonomy CICSyN The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Recharging Circuitry, MICAz sensor nodes, Low Power Design, Energy Harvest, Batteries
16Qiang Wang, Subodh Gupta, Jason Helge Anderson Clock power reduction for virtex-5 FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
16Abel G. Silva-Filho, Sidney M. L. Lima, F. C. L. Cox Low Power RTL Exploration Mechanism Based on the Cache Parameters. Search on Bibsonomy ReConFig The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Exploration Mechanism, NIOSII, FPGA, Embedded Systems, SoC, Low Power Design, Cache Memory
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