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Publication years (Num. hits)
1970-1983 (15) 1984-1989 (19) 1990-1992 (17) 1993-1995 (38) 1996 (16) 1997 (22) 1998-1999 (53) 2000 (30) 2001 (34) 2002 (49) 2003 (63) 2004 (62) 2005 (72) 2006 (86) 2007 (81) 2008 (77) 2009 (53) 2010 (33) 2011-2012 (21) 2013-2014 (20) 2015 (16) 2016-2017 (23) 2018 (15) 2019 (3)
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article(201) book(3) incollection(2) inproceedings(707) phdthesis(5)
Venues (Conferences, Journals, ...)
IPDPS(31) IEEE Trans. Computers(26) ISCA(26) ICS(23) Euro-Par(21) DATE(19) IEEE Trans. Parallel Distrib. ...(17) HPCA(16) DAC(14) ISLPED(14) PPOPP(14) ICPP(12) LCPC(12) IEEE PACT(11) MICRO(11) SC(11) More (+10 of total 302)
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Found 918 publication records. Showing 918 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
72Xiaogang Qiu, Michel Dubois Tolerating Late Memory Traps in Dynamically Scheduled Processors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
68Tsu-Ming Liu, Chen-Yi Lee Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF prediction, memory hierarchy, H.264/AVC, lookahead
67Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
63Kamen Yotov, Keshav Pingali, Paul Stodghill Automatic measurement of memory hierarchy parameters. Search on Bibsonomy SIGMETRICS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF hardware parameters, optimization, caches, measurement, memory hierarchy, autonomic systems, self-tuning, micro-benchmarks
63Xing Du, Xiaodong Zhang 0001, Zhichun Zhu Memory Hierarchy Considerations for Cost-Effective Cluster Computing. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Clusters, performance evaluation, memory hierarchy, cost model, SMP, workstations
59Mahmut T. Kandemir, Alok N. Choudhary Compiler-directed scratch pad memory hierarchy design and management. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF memory hierarchy, data reuse, scratch pad memory
54Steve Carr, Soner Önder A case for a working-set-based memory hierarchy. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF cache design, loop tiling
48Athanasios Milidonis, Nikolaos Alachiotis, Vasileios Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Abhishek Das, William J. Dally Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy. Search on Bibsonomy PACT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
42A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF memory hierarchy simulation, desktop PC, commodity chips, PC microcomputers, synthetic bus traces, dynamically scheduled superscalar microprocessor, performance evaluation, memory architecture
41Kamen Yotov, Thomas Roeder, Keshav Pingali, John A. Gunnels, Fred G. Gustavson An experimental comparison of cache-oblivious and cache-conscious programs. Search on Bibsonomy SPAA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF cache-conscious algorithms, memory hierarchy, memory bandwidth, memory latency, numerical software, cache-oblivious algorithms
41Keith D. Cooper, Timothy J. Harvey Compiler-Controlled Memory. Search on Bibsonomy ASPLOS The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
40Enric Herrero, José González, Ramon Canal Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF elastic cooperative caching, tiled microarchitectures, chip multiprocessors, memory hierarchy
40Yuying Wang, Xingshe Zhou Mutual Effect of Instruction Layout Optimization and Instruction Memory Hierarchy. Search on Bibsonomy ICPP Workshops The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Instruction Layout Optimization, Instruction Cache Miss Rate, Cache Memory Hierarchy
39Philip Machanick The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF low-power design, cache memories, virtual memory, microkernels, main memory
39José Leandro D. Mendes, Luiza M. N. Coutinho, Carlos A. P. S. Martins Web memory hierarchy learning and research environment. Search on Bibsonomy WCAE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Avi Mendelson Memory management challenges in the power-aware computing era. Search on Bibsonomy ISMM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Ozcan Ozturk 0001, Mahmut T. Kandemir Energy management in software-controlled multi-level memory hierarchies. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF software-managed memory, embedded systems
37Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapata Probabilistic Miss Equations: Evaluating Memory Hierarchy Performance. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF probabilistic miss estimation, Analytical modeling, performance prediction, memory hierarchy, compiler optimizations
37Andreas Moshovos, Gurindar S. Sohi Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. Search on Bibsonomy MICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF DEF-store-load-USE chains, address disambiguation, data cache access, data cache bandwidth requirements, data dependence prediction, inter-operation memory communication, memory dependences, memory hierarchy design, transient value cache, storage management, memory architecture, communication latency, instruction window, address calculation
37Arun K. Nanda, Lionel M. Ni MAD Kernels: An Experimental Testbed to Study Multiprocessor Memory System Behavior. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF memory access patterns, Performance evaluation, interconnection networks, memory hierarchy, shared-memory multiprocessors, resource contention, synchronization overhead
37Benny Thörnberg, Martin Palkovic, Qubo Hu, Leif Olsson, Per Gunnar Kjeldsberg, Mattias O'Nils, Francky Catthoor Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37John E. Savage, Mohammad Zubair A unified model for multicore architectures. Search on Bibsonomy IFMT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF multicore, memory hierarchy
37Tanja Van Achteren, Francky Catthoor, Rudy Lauwereins, Geert Deconinck Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Memory hierarchy, power consumption, data reuse
37Bithika Khargharia, Salim Hariri, Mazin S. Yousif An Adaptive Interleaving Technique for Memory Performance-per-Watt Management. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
37Zuo Wang, Feng Shi, Qi Zuo, Weixing Ji, Mengxiao Liu N-port memory mapping for LUT-based FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF logical-to-physical mapping, n-port memory, fpga, hierarchy
37Shuang Liang, Ranjit Noronha, Dhabaleswar K. Panda Swapping to Remote Memory over InfiniBand: An Approach using a High Performance Network Block Device. Search on Bibsonomy CLUSTER The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher A low-power memory hierarchy for a fully programmable baseband processor. Search on Bibsonomy WMPI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF baseband processor, multi-tasked processor, task interleaving, memory hierarchy, low-power memory
35Thomas Kistler, Michael Franz Automated data-member layout of help objects to improve memory-hierarchy performance. Search on Bibsonomy ACM Trans. Program. Lang. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF dynmaic data structures, memory-hierarchy optimization, dynamic optimization
35Martin C. Herbordt, Charles C. Weems An empirical study of datapath, memory hierarchy, and network in SIMD array architectures. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF SIMD array architectures, SIMD arrays, ENPASSANT, router network, local transfers, performance evaluation, performance, parallel architectures, broadcast, virtual machines, memory hierarchy, reduction, associativity, memory architecture, cache storage, simulation environment, datapath, block size
35Erik G. Hallnor, Steven K. Reinhardt A compressed memory hierarchy using an indirect index cache. Search on Bibsonomy WMPI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35Radomir Jakovljevic, Aleksandar Beric A method for improving the efficiency of a two-level memory hierarchy. Search on Bibsonomy SiPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Chia-Lin Yang, Alvin R. Lebeck A Programmable Memory Hierarchy for Prefetching Linked Data Structures. Search on Bibsonomy ISHPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
35Chuanjun Zhang, Frank Vahid Using a Victim Buffer in an Application-Specific Memory Hierarchy. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35Nancy M. Amato, Jack Perdue, Mark M. Mathis, Andrea Pietracaprina, Geppino Pucci Predicting Performance on SMPs. A Case Study: The SGI Power Challenge. Search on Bibsonomy IPDPS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Caches, Performance Modeling, Memory Hierarchy, SMPs
35Xiaogang Qiu, Michel Dubois Towards Virtually-Addressed Memory Hierarchies. Search on Bibsonomy HPCA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
35Xing Du, Xiaodong Zhang 0001 The Impact of Memory Hierarchies on Cluster Computing. Search on Bibsonomy IPPS/SPDP The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
33Xu Wang, Ge Gan, Joseph B. Manzano, Dongrui Fan, Shuxu Guo A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor. Search on Bibsonomy ICPADS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Kayvon Fatahalian, Daniel Reiter Horn, Timothy J. Knight, Larkhoon Leem, Mike Houston, Ji Young Park, Mattan Erez, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan Sequoia: programming the memory hierarchy. Search on Bibsonomy SC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors. Search on Bibsonomy ICPADS (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Peter Sanders 0001 Accessing Multiple Sequences Through Set Associative Caches. Search on Bibsonomy ICALP The full citation details ... 1999 DBLP  DOI  BibTeX  RDF multi merge, memory hierarchy, external memory algorithm, Set associative cache
33Xuejun Yang, Jing Du, Xiaobo Yan, Yu Deng 0001 Matrix-Based Programming Optimization for Improving Memory Hierarchy Performance on Imagine. Search on Bibsonomy ISPA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic HitME: low power Hit MEmory buffer for embedded systems. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
33Michael A. Bender, Ziyang Duan, John Iacono, Jing Wu A locality-preserving cache-oblivious dynamic dictionary. Search on Bibsonomy SODA The full citation details ... 2002 DBLP  BibTeX  RDF
31Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal Sidhwaney Memory Hierarchy Design for a Multiprocessor Look-up Engine. Search on Bibsonomy IEEE PACT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
31Akshat Verma, Sandeep Sen Combating I-O bottleneck using prefetching: model, algorithms, and ramifications. Search on Bibsonomy The Journal of Supercomputing The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Prediction sequence, Sorting, Prefetching, Memory hierarchy, External memory algorithms
31Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique
31Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF customized memory hierarchy, multiprocessor data reuse analysis, scratch pad memory management
31Chen Ding, Ken Kennedy The Memory Bandwidth Bottleneck and its Amelioration by a Compiler. Search on Bibsonomy IPDPS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF memory performance model, array reduction, store elimination, memory hierarchy, compiler optimizations, Memory bandwidth, loop fusion
31Henk L. Muller, Paul W. A. Stallard, David H. D. Warren The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison. Search on Bibsonomy PDP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios
31Gyungho Lee An assessment of COMA multiprocessors. Search on Bibsonomy IPPS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate
31Lamia Youseff, Keith Seymour, Haihang You, Jack J. Dongarra, Richard Wolski The impact of paravirtualized memory hierarchy on linear algebra computational kernels and software. Search on Bibsonomy HPDC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF paravirtualization, cloud computing, high performance, linear algebra, virtual machine monitors, blas, autotuning
31Bert Geelen, Gauthier Lafruit, Vissarion Ferentinos, Rudy Lauwereins, Diederik Verkest Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Eric Debes A new Petri net based model of data transfers in the PC workstation memory hierarchy for MPEG encoding. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
31Manman Ren, Ji Young Park, Mike Houston, Alex Aiken, William J. Dally A tuning framework for software-managed memory hierarchies. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF bulk decomposition, empirical tuning, software-managed memory hierarchy
31Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins Building the functional performance model of a processor. Search on Bibsonomy SAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF grid computing, parallel computing, distributed computing, performance modeling, memory hierarchy, heterogeneous computing, processor performance
30Radomir Jakovljevic, Aleksandar Beric N-meander scanning trace a method for the on-chip bandwidth reduction. Search on Bibsonomy ICIP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
30Rony Ghattas, Gregory S. Parsons, Alexander G. Dean Optimal Unified Data Allocation and Task Scheduling for Real-Time Multi-Tasking Systems. Search on Bibsonomy IEEE Real-Time and Embedded Technology and Applications Symposium The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Aleksandar Beric, Jef L. van Meerbergen, Gerard de Haan, Ramanathan Sethuraman Memory-Centric Video Processing. Search on Bibsonomy IEEE Trans. Circuits Syst. Video Techn. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
30Thomas R. Puzak, Allan Hartstein, Philip G. Emma, Viji Srinivasan, Arthur Nadas Pipeline spectroscopy. Search on Bibsonomy Experimental Computer Science The full citation details ... 2007 DBLP  DOI  BibTeX  RDF cost of a miss, probability transition matrix, cache, convex combination
30Michael A. Bender, Gerth Stølting Brodal, Rolf Fagerberg, Dongdong Ge, Simai He, Haodong Hu, John Iacono, Alejandro López-Ortiz The Cost of Cache-Oblivious Searching. Search on Bibsonomy FOCS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
29Guangming Tan, Dongrui Fan, Junchao Zhang, Andrew Russo, Guang R. Gao Experience on optimizing irregular computation for memory hierarchy in manycore architecture. Search on Bibsonomy PPOPP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF irregular computation., synchronization, memory hierarchy, percolation
29Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas A Dynamically Tunable Memory Hierarchy. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF High performance microprocessors, energy and performance of on-chip caches, memory hierarchy, reconfigurable architectures
29Neungsoo Park, Bo Hong, Viktor K. Prasanna Tiling, Block Data Layout, and Memory Hierarchy Performance. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Block data layout, TLB misses, memory hierarchy, tiling, cache misses
29W. Lynn Gallagher, Chuan-lin Wu Evaluation of a memory hierarchy for the MTS multithreaded processor. Search on Bibsonomy ICPADS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
29Wesley K. Kaplow, William Maniatty, Boleslaw K. Szymanski Impact of memory hierarchy on program partitioning and scheduling. Search on Bibsonomy HICSS (2) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF parallel program scheduling, nonlinear cache-miss rates, loop nest execution simulation, architecturally parameterized cache simulator, loop range, cache-miss ratio, loop interchange, iteration-space blocking, program runtime estimation, IBM 9076 SP1, SuperSPARC, scheduling, parallel programming, optimisation, memory hierarchy, processor scheduling, software performance evaluation, memory architecture, cache storage, program optimization, cache performance, program control structures, program partitioning, Intel i860
29Terry A. Welch Memory Hierarchy Configuration Analysis. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1978 DBLP  DOI  BibTeX  RDF speed-cost tradeoffs, Access time minimization, memory access probabilities, memory hierarchy analysis, memory performance bounds, memory systems
28Akshat Verma, Sandeep Sen Algorithmic Ramifications of Prefetching in Memory Hierarchy. Search on Bibsonomy HiPC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Erik G. Hallnor, Steven K. Reinhardt A Unified Compressed Memory Hierarchy. Search on Bibsonomy HPCA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Philip Machanick, Pierre Salverda, Lance Pompe Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy. Search on Bibsonomy ASPLOS The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
28Peng Li, Dongsheng Wang, Songliu Guo, Tao Tian, Weimin Zheng Live Range Aware Cache Architecture. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Live Range, Cache, Memory Hierarchy
28Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee Tolerating memory latency through push prefetching for pointer-intensive applications. Search on Bibsonomy TACO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF linked data structures, pointer-chasing, Prefetch, memory hierarchy
28Maciej Drozdowski, Pawel Wolniewicz Out-of-Core Divisible Load Processing. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF scheduling, performance evaluation, memory hierarchy, communication delays, Divisible load theory
28Vincent Loechner, Benoît Meister, Philippe Clauss Data Sequence Locality: A Generalization of Temporal Locality. Search on Bibsonomy Euro-Par The full citation details ... 2001 DBLP  DOI  BibTeX  RDF cache and TLB performance, parameterized polyhedra, Ehrhart polynomials, Memory hierarchy, temporal locality, loop nests
28Wei Xu, Jibang Liu, Tong Zhang 0002 Data manipulation techniques to reduce phase change memory write energy. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low power, phase change memory
28Shlomi Dolev, Reuven Yagel Memory Management for Self-stabilizing Operating Systems. Search on Bibsonomy Self-Stabilizing Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Changpeng Fang, Steve Carr, Soner Önder, Zhenlin Wang Instruction Based Memory Distance Analysis and its Application. Search on Bibsonomy IEEE PACT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Chris Gniady, Babak Falsafi Speculative Sequential Consistency with Little Custom Storage. Search on Bibsonomy IEEE PACT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
28Caroline Benveniste, Peter A. Franaszek, John T. Robinson Cache-Memory Interfaces in Compressed Memory Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF memory compression, performance analysis, trace-driven simulation, cache design, Memory system design
28Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran A novel instruction scratchpad memory optimization method based on concomitance metric. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Magnus Ekman, Per Stenström A Cost-Effective Main Memory Organization for Future Servers. Search on Bibsonomy IPDPS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
28Jason Hiser, Jack W. Davidson, David B. Whalley Fast, accurate design space exploration of embedded systems memory configurations. Search on Bibsonomy SAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF memory hierachy, embedded systems, performance estimation
28Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos E. Kozyrakis, Bruce McGaughy, David A. Patterson, Thomas E. Anderson, Katherine A. Yelick The Energy Efficiency of IRAM Architectures. Search on Bibsonomy ISCA The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
28Rohit Chandra, Anoop Gupta, John L. Hennessy Data Locality and Load Balancing in COOL. Search on Bibsonomy PPOPP The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
26Philip Machanick Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Sriram Krishnamoorthy, Ümit V. Çatalyürek, Jarek Nieplocha, Atanas Rountev, P. Sadayappan Data management and query - Hypergraph partitioning for automatic memory hierarchy management. Search on Bibsonomy SC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
26Evangelia Athanasaki, Kornilios Kourtis, Nikos Anastopoulos, Nectarios Koziris Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures. Search on Bibsonomy Panhellenic Conference on Informatics The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Abhishek Das, William J. Dally Stream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies. Search on Bibsonomy Euro-Par The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Stream Scheduling, Bulk Operations, Sequoia, GSOP Memory Hierarchy, Tunables, Software Pipelining
26Zhiyong Li 0002, Peter Mills, John H. Reif Models and resource metrics for parallel and distributed computation. Search on Bibsonomy HICSS (2) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF resource metrics, architectural details, generic parameters, network communication costs, LogP-HMM model, parameterized network model, sequential hierarchical memory model, multilevel memory, local cache, near-optimal sorting, parallel processing, parallel computation, distributed algorithms, distributed computation, resource allocation, sorting, fast Fourier transforms, parallel machines, memory hierarchy, cache storage, design principles, asynchrony, parallel models, input/output, synchronous models, fast Fourier transform algorithms
26Bob Janssens, W. Kent Fuchs The Performance of Cache-Based Error Recovery in Multiprocessors. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF cache-based error recovery performance, cache-based checkpointing, rollback error recovery, shared-memorymultiprocessors, inherent redundancy, computation state, rollback propagation, EncoreMultimax, recovery schemes, cache-based schemes, low performance overhead, checkpoint interval, performance evaluation, performance evaluation, virtual machines, multiprocessors, redundancy, memory hierarchy, shared memory systems, system recovery, buffer storage, parallel applications, cache coherence protocol, transient errors, cache replacement policy, address traces
26Murali Jayapala, Francisco Barat, Pieter Op de Beeck, Francky Catthoor, Geert Deconinck, Henk Corporaal A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
26Neungsoo Park, Bo Hong, Viktor K. Prasanna Analysis of Memory Hierarchy Performance of Block Data Layout. Search on Bibsonomy ICPP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
26Daniel Chaver, Christian Tenllado, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado -D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation. Search on Bibsonomy HiPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
26Timothy Sherwood, Brad Calder ToolBlocks: An Infrastructure for the Construction of Memory Hierarchy Analysis Tools (Research Note). Search on Bibsonomy Euro-Par The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
26Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan Compilation for explicitly managed memory hierarchies. Search on Bibsonomy PPOPP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF bulk operations, software-managed memory hierarchy
26Xiaogang Qiu, Michel Dubois Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF dynamic address translation, virtual-address caches, simulations, Multiprocessors, distributed shared memory, virtual memory
26Ping Zhou, Bo Zhao 0007, Jun Yang 0002, Youtao Zhang A durable and energy efficient main memory using phase change memory technology. Search on Bibsonomy ISCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low power, phase change memory, endurance
26Haipeng Cheng, Zheng Chen, Bei Hua, Xinan Tang Scalable packet classification using interpreting: a cross-platform multi-core solution. Search on Bibsonomy PPOPP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF architecture, multithreading, network processor, packet classification, thread-level parallelism, embedded system design
26Jayaprakash Pisharath, Alok N. Choudhary An integrated approach to reducing power dissipation in memory hierarchies. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF RDRAM, dynamic cache, energy-saver buffers (ESB), power, integrated approach, energy-delay product
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