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Found 1604 publication records. Showing 1604 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
132Jian Wang, Guang R. Gao Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops. Search on Bibsonomy CC The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Very Long Instruction Word(VLIW), Instruction-Level Parallelism, Software Pipelining, Superscalar, Nested Loop, Loop Scheduling, Fine-Grain Parallelism
131Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou 0001 Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
113Monica S. Lam Software pipelining: an effective scheduling technique for VLIW machines (with retrospective) Search on Bibsonomy Best of PLDI The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
110João M. P. Cardoso Dynamic loop pipelining in data-driven architectures. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF compilation, reconfigurable computing, software pipelining, dataflow, data-driven architectures
93Reese B. Jones, Vicki H. Allan Software pipelining: a comparison and improvement. Search on Bibsonomy MICRO The full citation details ... 1990 DBLP  BibTeX  RDF recognition of parallelism, software pipelining, operation scheduling
80Miodrag Potkonjak, Jan M. Rabaey Optimizing throughput and resource utilization using pipelining: Transformation based approach. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
79Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin Design tradeoffs in high speed multipliers and FIR filters. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
77Han-Saem Yun, Jihong Kim, Soo-Mook Moon Time Optimal Software Pipelining of Loops with Control Flows. Search on Bibsonomy International Journal of Parallel Programming The full citation details ... 2003 DBLP  DOI  BibTeX  RDF compiler optimization, instruction-level parallelism, software pipelining, VLIW
72Mark G. Stoodley, Corinna G. Lee Software Pipelining Loops with Conditional Branches. Search on Bibsonomy MICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
68Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao Single-dimension software pipelining for multidimensional loops. Search on Bibsonomy TACO The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Software pipelining, loop transformation, modulo scheduling
68Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
65Smita Bakshi, Daniel Gajski Performance-constrained hierarchical pipelining for behaviors, loops, and operations. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF DSP (digital signal processing) systems, hierarchical pipelining, pipelined systems, scheduling, component selection, loop pipelining
64Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung Outer Loop Pipelining for Application Specific Datapaths in FPGAs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
64Pallav Gupta, Niraj K. Jha An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
64Bogong Su, Jian Wang, Erh-Wen Hu, Joseph B. Manzano Software De-Pipelining Technique. Search on Bibsonomy SCAM The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Haitao Wei, Junqing Yu, Huafei Yu, Guang R. Gao Minimizing communication in rate-optimal software pipelining for stream programs. Search on Bibsonomy CGO The full citation details ... 2010 DBLP  DOI  BibTeX  RDF dfbrook, multi-core, software pipelining, cell processor, stream programs
60Won So, Alexander G. Dean Complementing software pipelining with software thread integration. Search on Bibsonomy LCTES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF TI C6000, DSP, software pipelining, VLIW, stream programming, coarse-grain parallelism, software thread integration
56Dragan Milicev, Zoran Jovanovic A Formal Model of Software Pipelining Loops with Conditions. Search on Bibsonomy IPPS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF software pipelining loops, PSP model, parallel programming, finite state machine, formal model, software pipelining, parallelizing loops, conditional branches
56Mohammed Fellahi, Albert Cohen 0001 Software Pipelining in Nested Loops with Prolog-Epilog Merging. Search on Bibsonomy HiPEAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
56Lingfang Zeng, Dan Feng 0001, Fang Wang 0001 Pipelining Network Storage I/O. Search on Bibsonomy International Conference on Computational Science (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
56Guy E. Blelloch, Margaret Reid-Miller Pipelining with Futures. Search on Bibsonomy Theory Comput. Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
56Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
56Monica S. Lam Software Pipelining: An Effective Scheduling Technique for VLIW Machines. Search on Bibsonomy PLDI The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
54Xue Yang, Nitin H. Vaidya, Priya Ravichandran Split-Channel Pipelined Packet Scheduling for Wireless Networks. Search on Bibsonomy IEEE Trans. Mob. Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF bandwidth-independent overhead, bandwidth-dependent overhead, access energy cost, packet access delay, wireless LANs, pipelining, IEEE 802.11, multihop networks, channel utilization, Multiple access control (MAC)
54Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications. Search on Bibsonomy ICPP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Scheduling, Software pipelining, Retiming, DSP processors
52Takuya Miyamaru, Hiroshi Mineno, Yoshiaki Terashima, Yuichi Tokunaga, Tadanori Mizuno State-Based Pipelining for Reprogramming Wireless Sensor Networks. Search on Bibsonomy KES (3) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Wireless sensor network, Pipelining, Reprogramming
52Yuan-man Tong, Zhiying Wang, Kui Dai, Hongyi Lu Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining. Search on Bibsonomy Inscrypt The full citation details ... 2006 DBLP  DOI  BibTeX  RDF WDDL, power analysis resistant, block cipher, design flow, Wave-pipelining
52Noureddine Chabini, Wayne H. Wolf An approach for integrating basic retiming and software pipelining. Search on Bibsonomy EMSOFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF embedded systems, system-on-chip, timings, instruction-level parallelism, software pipelining, VLIW, retiming, superscalar processor, peak power, code size
52Akshay Sharma, Carl Ebeling, Scott Hauck PipeRoute: a pipelining-aware router for FPGAs. Search on Bibsonomy FPGA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF BFS, PipeRoute, retimed circuits, routing, pipelining, minimum spanning tree, retiming, pipelined circuits
52Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation
52William Chow, Jonathan Rose EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. Search on Bibsonomy FPGA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF event horizon, manual placement and pipelining, FPGA, programmable logic
52Han-Saem Yun, Jihong Kim, Soo-Mook Moon Optimal software pipelining of loops with control flows. Search on Bibsonomy ICS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF instruction-level parallelism, software pipelining, VLIW
52Jiang Xu 0001, Wayne H. Wolf Wave pipelining for application-specific networks-on-chips. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF system-on-chip (SoC), interconnection, networks-on-chip (NoC), wave pipelining, coupling capacitance
52Iffat H. Kazi, David J. Lilja Coarse-Grained Thread Pipelining: A Speculative Parallel Execution Model for Shared-Memory Multiprocessors. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Runtime parallelization, thread pipelining, superthreaded architecture, shared-memory multiprocessors, speculative execution, coarse-grained parallelization
52Elana D. Granston, Eric Stotzer, Joe Zbiciak Software Pipelining Irregular Loops on the TMS320C6000 VLIW DSP Architecture. Search on Bibsonomy LCTES/OM The full citation details ... 2001 DBLP  DOI  BibTeX  RDF WHILE loops, software pipelining, digital signal processors, VLIW architectures
52G. Enrique Fernandez, R. Sridhar Dual rail static CMOS architecture for wave pipelining. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
52Alexander Aiken, Alexandru Nicolau, Steven Novack Resource-Constrained Software Pipelining. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Software pipelining, instruction scheduling, program optimization, global scheduling, fine-grain parallelism
52Jian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis Software pipelining with register allocation and spilling. Search on Bibsonomy MICRO The full citation details ... 1994 DBLP  DOI  BibTeX  RDF instruction-level parallelism, register allocation, software pipelining, loop scheduling, register spilling
52Barron C. Housel Pipelining: A Technique for Implementing Data Restructurers. Search on Bibsonomy ACM Trans. Database Syst. The full citation details ... 1979 DBLP  DOI  BibTeX  RDF database conversion, pipelining, deadlock, process scheduling, data translation
50G. Seetharaman, B. Venkataramani Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. Search on Bibsonomy TRETS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA
50SangMin Shim, Soo-Mook Moon Split-Path Enhanced Pipeline Scheduling. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multipath loops, enhanced pipeline scheduling, all-path pipelining, Instruction-level parallelism, software pipelining, modulo scheduling
50Rajesh S. Parthasarathy, Ramalingam Sridhar Double Pass Transistor Logic for High Performance Wave Pipeline Circuits. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
50Debabrata Ghosh, S. K. Nandy Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
47Akshay Sharma, Carl Ebeling, Scott Hauck PipeRoute: a pipelining-aware router for reconfigurable architectures. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Daehong Kim, Dongwan Shin, Kiyoung Choi Pipelining with common operands for power-efficient linear systems. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong Microarchitecture evaluation with floorplanning and interconnect pipelining. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Naohiro Ishii, Hiroaki Ogi, Tsubasa Mochizuki, Kazunori Iwata 0001 Parallelism Improvements of Software Pipelining by Combining Spilling with Rematerialization. Search on Bibsonomy KES (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. Search on Bibsonomy CGO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Haibo Lin, Wenlong Li, Zhizhong Tang Overcoming Static Register Pressure for Software Pipelining in the Itanium Architecture. Search on Bibsonomy APPT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller A novel approach based on genetic algorithm for pipelining of recursive filters. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
47Han-Saem Yun, Jihong Kim, Soo-Mook Moon A First Step Towards Time Optimal Software Pipelining of Loops with Control Flows. Search on Bibsonomy CC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
47Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith Timing constraints for high-speed counterflow-clocked pipelining. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
47Alejandro P. Buchmann, Ming-Chuan Wu Supporting Group-By and Pipelining in Bitmap-Enabled Query Processors. Search on Bibsonomy SOFSEM The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
47Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu Wave-pipelining: a tutorial and research survey. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
47Fabian Klass, Michael J. Flynn, A. J. van de Goor Fast multiplication in VLSI using wave pipelining techniques. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
46Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor A comparative evaluation of software techniques to hide memory latency. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
44Hui Liu 0006, Zili Shao, Meng Wang 0005, Junzhao Du, Chun Jason Xue, Zhiping Jia Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems. Search on Bibsonomy Signal Processing Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming
44Hyeong Seog Kim, In Soon Cho, Heon Young Yeom A Task Pipelining Framework for e-Science Workflow Management Systems. Search on Bibsonomy CCGRID The full citation details ... 2008 DBLP  DOI  BibTeX  RDF task pipelining, workflow manager
44Sebastian Winkel, Rakesh Krishnaiyer, Robyn Sampson Latency-tolerant software pipelining in a production compiler. Search on Bibsonomy CGO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF latency-tolerant scheduling, load clustering, compiler, code generation, prefetching, software pipelining, modulo scheduling, memory latency, memory-level parallelism, itanium, epic
44Xue Yang, Nitin H. Vaidya A Wireless MAC Protocol Using Implicit Pipelining. Search on Bibsonomy IEEE Trans. Mob. Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF access energy cost, packet access delay, wireless LANs, pipelining, IEEE 802.11, multihop networks, channel utilization, Multiple access control (MAC)
44Mario R. Casu, Luca Macchiarulo Floorplan assisted data rate enhancement through wire pipelining: a real assessment. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF through-put, systems-on-chip, floorplanning, wire pipelining
44Jason Cong, Yiping Fan, Zhiru Zhang Architecture-level synthesis for automatic interconnect pipelining. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding
44Cagdas Akturan, Margarida F. Jacome RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors. Search on Bibsonomy CODES The full citation details ... 2001 DBLP  DOI  BibTeX  RDF embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors
44Pierre-Yves Calland, Alain Darte, Yves Robert Circuit Retiming Applied to Decomposed Software Pipelining. Search on Bibsonomy IEEE Trans. Parallel Distrib. Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF circuit retiming, Software pipelining, list scheduling, modulo scheduling, cyclic scheduling
44Tao Yu, Zhizhong Tang, Chihong Zhang, Jun Luo Control Mechanism for Software Pipelining on Nested Loop. Search on Bibsonomy APDC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF ILSP, software pipelining, VLIW, dataflow, nested loop
42KyungHi Chang, XuDuan Lin Ultra-high-speed digital filtering algorithm for video signal processing. Search on Bibsonomy ICIP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF ultra-high-speed digital filtering algorithm, improved minimum-order augmented pipelining, IMAP algorithm, clustered look-ahead technique, augmented pipelining order, undesirable quantization effects, 1-D IMAP digital filter, 2-D structure, bandwidth reduction algorithm, motion estimation, motion estimation, pipeline processing, minimization, minimisation, video signal processing, video signal processing, interference suppression, two-dimensional digital filters, spatio-temporal filtering
42Siamak Arya, Howard Sachs, Sreeram Duvvuru An architecture for high instruction level parallelism. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, branches, program control structures, registers, functional units, multiple instructions, conditional execution
42Reese B. Jones, Vicki H. Allan Software Pipelining: An Evaluation of Enhanced Pipelining. Search on Bibsonomy MICRO The full citation details ... 1991 DBLP  DOI  BibTeX  RDF software pipelining, instruction scheduling, loop optimization, fine-grain parallelism
41Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha Timing Optimization of Nested Loops Considering Code Size for DSP Applications. Search on Bibsonomy ICPP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Ching-Wen Chen, Chuan-Chi Weng, Po-Jung Chen Design of a Low-Power and Low-Latency MAC Protocol with Nodes Grouping and Transmission Pipelining in Wireless Sensor Networks. Search on Bibsonomy VTC Spring The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Florent Blachot, Benoît Dupont de Dinechin, Guillaume Huard SCAN: A Heuristic for Near-Optimal Software Pipelining. Search on Bibsonomy Euro-Par The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip. Search on Bibsonomy ASAP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Xiaoyao Liang, Akshay Athalye, Sangjin Hong Equalizing data-path for processing speed determination in block level pipelining. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan, Alban Douillet, Guang R. Gao Single-Dimension Software Pipelining for Multi-Dimensional Loops. Search on Bibsonomy CGO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Jia Di, Jiann S. Yuan, Ronald F. DeMara High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
39Gang-Ryung Uh Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer. Search on Bibsonomy SCOPES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
39Kalyan Muthukumar, Gautam Doshi Software Pipelining of Nested Loops. Search on Bibsonomy CC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
39Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. Search on Bibsonomy IEEE PACT The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
39Toshinori Sato A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism. Search on Bibsonomy EUROMICRO The full citation details ... 1999 DBLP  DOI  BibTeX  RDF instruction reissue, instruction window design, instruction level parallelism, data speculation, dynamic instruction scheduling
39Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses Some experiments about wave pipelining on FPGA's. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
39Chihong Zhang, Zhizhong Tang An Improvement on Data Dependence Analysis Supporting Software Pipelining Technique. Search on Bibsonomy APDC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
39Jian-Feng Shi, Liang-Fang Chao Resource-Constrained Algebraic Transformation for Loop Pipelining. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
39Derek C. Wong, Giovanni De Micheli, Michael J. Flynn Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
39Vincent Van Dongen, Guang R. Gao, Qi Ning A Polynomial Time Method for Optimal Software Pipelining. Search on Bibsonomy CONPAR The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
39Bogong Su, Jian Wang, Zhizhong Tang, Wei Zhao, Yimin Wu A software pipelining based VLIW architecture and optimizing compiler. Search on Bibsonomy MICRO The full citation details ... 1990 DBLP  BibTeX  RDF
39Guang R. Gao, Herbert H. J. Hum, Yue-Bong Wong Towards efficient fine-grain software pipelining. Search on Bibsonomy ICS The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
39Alexander Aiken, Alexandru Nicolau Perfect Pipelining: A New Loop Parallelization Technique. Search on Bibsonomy ESOP The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
37Hongbo Rong, Alban Douillet, Guang R. Gao Register allocation for software pipelined multi-dimensional loops. Search on Bibsonomy PLDI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF register allocation, software pipelining
37Pradeep Kumar Mishra Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems. Search on Bibsonomy CHES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Jacobian coordinates, pipelining, Elliptic curve cryptosystems, scalar multiplication
37Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu Unroll-Based Copy Elimination for Enhanced Pipeline Scheduling. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF enhanced pipeline scheduling, unrolling, modulo variable expansion, iterated coalescing, register allocation, Software pipelining, modulo scheduling, renaming, coalescing
37Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger An ASIC Implementation of the AES SBoxes. Search on Bibsonomy CT-RSA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF standard-cell design, scalability, Very Large Scale Integration (VLSI), pipelining, Advanced Encryption Standard (AES), Application Specific Integrated Circuit (ASIC), inversion, finite field arithmetic
37G. X. Tyson, M. Smelyanskyi, Edward S. Davidson Evaluating the Use of Register Queues in Software Pipelined Loops. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF modulo variable expansion, rotating register file, register queues, register connection, Software pipelining, VLIW
35Jean-Baptiste Tristan, Xavier Leroy A simple, verified validator for software pipelining. Search on Bibsonomy POPL The full citation details ... 2010 DBLP  DOI  BibTeX  RDF software pipelining, translation validation, verified compilers, symbolic evaluation
35Ram Rangan, Neil Vachharajani, Guilherme Ottoni, David I. August Performance scalability of decoupled software pipelining. Search on Bibsonomy TACO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Decoupled software pipelining, performance analysis
35Sevin Fide, Stephen Jenks A middleware approach for pipelining communications in clusters. Search on Bibsonomy Cluster Computing The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Cluster communications, Middleware, MPI, Pipelining
35Sid Ahmed Ali Touati On the Periodic Register Need in Software Pipelining. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Periodic Register Requirement, MAXLIVE, Periodic Register Sufficiency, Stage Scheduling, Instruction Level Parallelism, Software Pipelining
35Anuja Jayraj Thakkar, Abdel Ejnioui Pipelining of double precision floating point division and square root operations. Search on Bibsonomy ACM Southeast Regional Conference The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FPGA, pipelining, floating point, division, square root
35Shih-Hao Wang, Wen-Hsiao Peng, Yuwen He, Guan-Yi Lin, Cheng-Yi Lin, Shih-Chien Chang, Chung-Neng Wang, Tihao Chiang A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2005 DBLP  DOI  BibTeX  RDF advanced video coding (AVC), joint video team (JVT), software-hardware co-implementation, MB level pipelining, H.264, MPEG-4, task partition
35Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multiphase, sequential circuit, software pipelining, clock, Retiming
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