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Searching for phrase power consumption (changed automatically) with no syntactic query expansion in all metadata.

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1977-1992 (15) 1993-1994 (21) 1995 (35) 1996 (38) 1997 (55) 1998 (84) 1999 (164) 2000 (155) 2001 (198) 2002 (334) 2003 (453) 2004 (520) 2005 (801) 2006 (918) 2007 (861) 2008 (781) 2009 (450) 2010 (203) 2011 (137) 2012 (137) 2013 (160) 2014 (169) 2015 (155) 2016 (165) 2017 (124) 2018 (134) 2019 (21)
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article(1455) incollection(10) inproceedings(5808) phdthesis(15)
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ISCAS(367) IEEE Trans. VLSI Syst.(192) DATE(168) ISLPED(164) VLSI Design(151) DAC(143) ISCAS (1)(140) ASP-DAC(126) PATMOS(119) IEEE Trans. on CAD of Integrat...(112) ACM Great Lakes Symposium on V...(109) ICCD(92) ISCAS (4)(87) ISCAS (5)(86) IPDPS(84) ISQED(83) More (+10 of total 1218)
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Found 7288 publication records. Showing 7288 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
82Avi Mendelson Memory management challenges in the power-aware computing era. Search on Bibsonomy ISMM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
64Hangu Yeo, Yu Hen Hu A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF matching criterion, real-time block based motion estimation, video signals, binary level matching criterion, bit-wise comparison, processor level design, total power consumption, motion estimation, power consumption, power consumption, video signal processing, combinational logic, low power architecture
63Keith Boyle, Sai Mohan Kilambi, Rafal Dlugosz, Kris Iniewski, Vincent C. Gaudet An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters. Search on Bibsonomy SiPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
60Aqeel Mahesri, Vibhore Vardhan Power Consumption Breakdown on a Modern Laptop. Search on Bibsonomy PACS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
57William Lloyd Bircher, Lizy K. John Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power sensing hardware, complete system power estimation, microprocessor performance event, microprocessor performance counter, online measurement, complete system power consumption, microprocessor power, on-chip performance event counter, system power consumption estimation, power model
57Wesley M. Felter, Karthick Rajamani, Tom W. Keller, Cosmin Rusu A performance-conserving approach for reducing peak power consumption in server systems. Search on Bibsonomy ICS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF power management, power modeling, processor simulation
57Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung Word-length selection for power minimization via nonlinear optimization. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF word length, synthesis, signal processing, Power consumption, power consumption, bitwidth
56Jaume A. Segura, Miquel Roca, Diego Mateo, Antonio Rubio An approach to dynamic power consumption current testing of CMOS ICs. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current
55Le Yan, Jiong Luo, Niraj K. Jha Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
55Minjie Xu, Zhaoguang Hu, Xiaoyou Jiao, Junyong Wu A Hybrid Social Model for Simulating the Effects of Policies on Residential Power Consumption. Search on Bibsonomy IDEAL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Residential power consumption, Power price policy, Saving electricity, Social influence model, Multi-agent systems (MAS)
54Chun-Hao Hsu, Jian Jhen Chen, Shiao-Li Tsao Evaluation and modeling of power consumption of a heterogeneous dual-core processor. Search on Bibsonomy ICPADS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
54Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña Power Consumption Management on FPGAs. Search on Bibsonomy CONIELECOMP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Genetic Algorithms, Field Programmable Gate Array, Power Consumption, Partial Reconfiguration, Circuit Design
54Ching-Wen Chen, Chang-Jung Ku, Chih-Hung Chang Designing a High Performance and Low Energy-Consuming Embedded System with Considering Code Compressed Environments. Search on Bibsonomy RTCSA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF decompression engine, performance, Embedded system, locality, power consumption, code compress
51Anand Raghunathan, Sujit Dey, Niraj K. Jha Register-transfer level estimation techniques for switching activity and power consumption. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs
51Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
50José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Atila Alvandpour, Per Larsson-Edefors, Christer Svensson Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. Search on Bibsonomy ISLPED The full citation details ... 1998 DBLP  DOI  BibTeX  RDF short-circuit current, power consumption, power estimation
49Roger D. Chamberlain, Eric Hemmeter, Robert Morley, Jason White Modeling the Power Consumption of Audio Signal Processing Computations Using Customized Numerical Representations. Search on Bibsonomy Annual Simulation Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF numerical representation, power consumption, audio signal processing
49Stefan Gerstendörfer, Hans-Joachim Wunderlich Minimized Power Consumption for Scan-Based BIST. Search on Bibsonomy J. Electronic Testing The full citation details ... 2000 DBLP  DOI  BibTeX  RDF build-in self-test (BIST), power consumption
49S. C. Prasad, Kaushik Roy 0001 Circuit optimization for minimisation of power consumption under delay constraint. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
49Joep L. W. Kessels VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes
47Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan Power emulation: a new paradigm for power estimation. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels
46Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF supply voltage scaling, performance, power consumption, CMOS, retiming, digital design
46Jorgen Peddersen, Sri Parameswaran CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF dynamic power optimization, CLIPPER, counter-based low impact processor, run-time power optimization, power consumption, energy consumption
46Takuro Inoue, Ailixier Aikebaier, Tomoya Enokido, Makoto Takizawa 0001 A Power Consumption Model of a Storage Server. Search on Bibsonomy NBiS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF Storage-based Applications, Power consumption model, Power consumption, Digital ecosystem
44Enric Musoll Speculating to reduce unnecessary power consumption. Search on Bibsonomy ACM Trans. Embedded Comput. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low-power microarchitectures, Low-power design
43Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Meira Jr., Ricardo Bianchini Limiting the power consumption of main memory. Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power and energy management, performance, main memory
43Kanishka Lahiri, Anand Raghunathan Power analysis of system-level on-chip communication architectures. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
42Anja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken The challenges of implementing fine-grained power gating. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF leakage power minimization, analysis, power management, register-transfer-level, power modeling, power gating
42Yen-Jun Chen, Ching-Hsien Hsu, Kuan-Ching Li, Hsi-Ya Chang, Shuen-Tai Wang Power Consumption Optimization of MPI Programs on Multi-core Clusters. Search on Bibsonomy Infoscale The full citation details ... 2009 DBLP  DOI  BibTeX  RDF MPI, cluster Computing, Power Consumption, multi-core processor
42Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
42Le Yan, Jiong Luo, Niraj K. Jha Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
42Terry Todd, Frazer Bennett, Alan Jones Low power rendezvous in embedded wireless networks. Search on Bibsonomy MobiHoc The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
42Marius Marcu, Dacian Tudor, Sebastian Fuicu Power efficiency analysis of multimedia secured mobile applications. Search on Bibsonomy IWCMC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF encoding/decoding, encryption/decryption, mobile devices, energy efficiency, wireless communication, power consumption, multimedia applications
42Lei Liu 0021, Guanhua Yan, Xinwen Zhang, Songqing Chen VirusMeter: Preventing Your Cellphone from Spies. Search on Bibsonomy RAID The full citation details ... 2009 DBLP  DOI  BibTeX  RDF mobile malware, mobile device security, anomaly detection, power consumption
42Jürgen Becker, Michael Hübner, Michael Ullmann Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Virtex FPGA, runtime reconfiguration, power consumption
41Anand Raghunathan, Sujit Dey, Niraj K. Jha High-level macro-modeling and estimation techniques for switching activity and power consumption. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Miriam Allalouf, Yuriy Arbitman, Michael Factor, Ronen I. Kat, Kalman Z. Meth, Dalit Naor Storage modeling for power estimation. Search on Bibsonomy SYSTOR The full citation details ... 2009 DBLP  DOI  BibTeX  RDF modeling, power, storage
41Jaehoon Jung, Seungmoon Choi Perceived Magnitude and Power Consumption of Vibration Feedback in Mobile Devices. Search on Bibsonomy HCI (2) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Vibration feedback, vibration motor, perceived magnitude, mobile device, power consumption
41Terry Tao Ye, Giovanni De Micheli, Luca Benini Analysis of power consumption on switch fabrics in network routers. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF interconnect networks, systems on chip, networks on chip, power consumption
41Manjit Borah, Mary Jane Irwin, Robert Michael Owens Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
41Erik Larsson, Zebo Peng Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF test set selection, TAM design, power consumption, hot-spots, Test scheduling, design exploration
41Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou A power modeling and characterization method for the CMOS standard cell library. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF power characterization, power consumption, power estimation
41Min Li, Xiaobo Wu, Menglian Zhao, Hui Wang, Xiaolang Yan Power Consumption of Wireless NIC and Its Impact on Joint Routing and Power Control in Ad Hoc Network. Search on Bibsonomy EUC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
40Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
40Ying-Wen Bai Optimum Information Queue Lengths in Semi-Batch Power Management Methods for a Palmtop Multimedia Terminal. Search on Bibsonomy ECBS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Machine State, Power Consumption, Queueing Model
40Ahmad Patooghy, Mahdi Fazeli, Seyed Ghassem Miremadi A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips. Search on Bibsonomy PRDC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF SEU-Tolerance, Power Consumption, NoC
40Howon Kim, Mun-Kyu Lee, Dong Kyue Kim, Sang-Kyoon Chung, Kyoil Chung Design and Implementation of Crypto Co-processor and Its Application to Security Systems. Search on Bibsonomy CIS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Crypto Algorithm, Power Consumption, Crypto Coprocessor
40Mladen Nikitovic, Mats Brorsson An adaptive chip-multiprocessor architecture for future mobile terminals. Search on Bibsonomy CASES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF chip-multiprocessor (CMP), power consumption, mobile terminals, energy-aware scheduling
39Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye A technique to determine power-efficient, high-performance superscalar processors. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
39Jindrich Sadil Neural models predicting traction power consumption: support of e-energy telematic systems. Search on Bibsonomy EATIS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF traction power consumption, artificial neural networks, prediction models
39Sotaro Ohara, Makoto Suzuki, Shunsuke Saruwatari, Hiroyuki Morikawa A Prototype of a Multi-core Wireless Sensor Node for Reducing Power Consumption. Search on Bibsonomy SAINT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF multi-core CPU, sensor network, hard real-time, low power consumption
39Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi 0001 A fast clock scheduling for peak power reduction in LSI. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF general-synchronous framework, peak power reduction, power consumption estimation, clock scheduling
39Lijun Gao, Keshab K. Parhi Models for Architectural Power and Power Grid Noise Analysis on Data Bus. Search on Bibsonomy VLSI Signal Processing The full citation details ... 2006 DBLP  DOI  BibTeX  RDF augmented DBT model, SCTA model, STCTA model, power consumption, switching activity, power spectrum, transition probability, power grid noise, transition activity
38Diana Bautista, Julio Sahuquillo, Houcine Hassan, Salvador Petit, José Duato Dynamic task set partitioning based on balancing memory requirements to reduce power consumption. Search on Bibsonomy ICS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF scheduling, real-time, multithreaded, multicore, power-aware, coarse-grain
38Kanupriya Gulati, Sunil P. Khatri, Peng Li Closed-loop modeling of power and temperature profiles of FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF sub-threshold leakage, dynamic power
38Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Inki Hong, Miodrag Potkonjak Power optimization in disk-based real-time application specific systems. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF design process abstractions, disk data assignment, electronic components, magnetic disks, mechanical-electronic subsystems, power consumption model, real-time application specific systems, task scheduling, power optimization, power reduction, power minimization, magnetic disc storage, disk drives
38Tajana Simunic, Stephen P. Boyd Managing Power Consumption in Networks on Chip. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
38Man Lung Mui, Kaustav Banerjee, Amit Mehrotra Supply and power optimization in leakage-dominant technologies. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Alex Shye, Benjamin Scholbrock, Gokhan Memik Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
38Jian-Jia Chen, Lothar Thiele Energy-efficient scheduling on homogeneous multiprocessor platforms. Search on Bibsonomy SAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF static power consumption, dynamic voltage scaling, real-time scheduling, task partitioning
38Tao Li 0006, Lizy Kurian John Run-time modeling and estimation of operating system power consumption. Search on Bibsonomy SIGMETRICS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low power, operating system, power estimation
38Minoru Etoh, Tomoyuki Ohya, Yuji Nakayama Energy Consumption Issues on Mobile Network Systems. Search on Bibsonomy SAINT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Moble Network, CO2, Power Consumption, Battery, Green Network
37Li Shang, Li-Shiuan Peh, Niraj K. Jha PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF BIST Design, Test, Low-power Design, Energy Consumption
37Inwhee Joe, Won-Tae Kim, Seokjoon Hong A Network Selection Algorithm considering Power Consumption in Hybrid Wireless Networks. Search on Bibsonomy ICCCN The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Yu Hu, Qing Li 0001, C.-C. Jay Kuo Run-Time Power Consumption Modeling for Embedded Multimedia Systems. Search on Bibsonomy RTCSA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
37Kartik Mohanram, Nur A. Touba Lowering power consumption in concurrent checkers via input ordering. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena Power Consumption Reduction Through Dynamic Reconfiguration. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
37Kamal S. Khouri, Niraj K. Jha Leakage power analysis and reduction during behavioral synthesis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Jinha Park, Sungjoo Yoo, Sunggu Lee, Chanik Park Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems. Search on Bibsonomy SEUS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low power states, measurement, power consumption, dynamic power management, Solid state disk, trace-based simulation
37Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box. Search on Bibsonomy Signal Processing Systems The full citation details ... 2008 DBLP  DOI  BibTeX  RDF substitution box (S-box), inversion in the finite field GF($28$), standard cell implementation, Advanced Encryption Standard (AES), power consumption, silicon area, critical path delay
37Daniel L. Stasiak, Rajat Chaudhry, Dennis Cox, Stephen D. Posluszny, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Michael Wang 0001 Cell Processor Low-Power Design Methodology. Search on Bibsonomy IEEE Micro The full citation details ... 2005 DBLP  DOI  BibTeX  RDF VLSI, design methodology, Cell processor, low power consumption
37Anantha Chandrakasan Ultra low power digital signal processing. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
37Anand Raghunathan, Niraj K. Jha An iterative improvement algorithm for low power data path synthesis. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Low power VLSI design, Power consumption, Behavioral synthesis
36Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson Transition-activity aware design of reduction-stages for parallel multipliers. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power consumption, parallel multiplier, partial product reduction, transition activity
36Juan Chen, Yong Dong, Huizhan Yi, Xuejun Yang Power Consumption Analysis of Embedded Multimedia Application. Search on Bibsonomy ICESS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Ramon Bertran, Marc González, Xavier Martorell, Nacho Navarro, Eduard Ayguadé Decomposable and responsive power models for multicore processors using performance counters. Search on Bibsonomy ICS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF power estimation, performance counters
36Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau A predictive decode filter cache for reducing power consumption in embedded processors. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Cache, embedded processors, power optimization
35Meikel Poess, Raghunath Othayoth Nambiar A power consumption analysis of decision support systems. Search on Bibsonomy WOSP/SIPEW The full citation details ... 2010 DBLP  DOI  BibTeX  RDF performance tuning and optimization, power and performance, use of benchmarks in industry and academia, energy efficiency, benchmarking, software performance testing
35Dominic A. Antonelli, Alan Jay Smith, Jan-Willem van de Waerdt Power consumption and reduction in a real, commercial multimedia core. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF tm3270, multimedia, power, energy, compiler optimization, cache memory, embedded processor
35Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Yung-Hsiang Lu, Giovanni De Micheli Comparing System-Level Power Management Policies. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
35Muhammed Salamah, Zuhair Abushaaban An adaptive transmission technique for low power consumption in wireless sensor networks. Search on Bibsonomy IWCMC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF radio propagation models, wireless sensor networks, power consumption, adaptive transmission
35Enrico Macii, Massimo Poncino Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
35Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Robert G. Knobel Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Gilberto Contreras, Margaret Martonosi Power prediction for intel XScale processors using performance monitoring unit events. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF XScale, power estimation, power modeling, hardware performance counters
35Ivo Bolsens Challenges and Opportunities for FPGA Platforms. Search on Bibsonomy FPL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
35Rama Sangireddy Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Wide-issue processors, integer pipeline, rename logic complexity, front-end power consumption
35Weidong Wu, Jian Shi, Ling Zuo, Bingxin Shi Power-Efficient TCAMS for Bursty Access Patterns. Search on Bibsonomy IEEE Micro The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Routing, power consumption, Access pattern, TCAM
34Ying-Wen Bai, Chun-Yang Tsai Design and implementation of a low-power workstation. Search on Bibsonomy CCECE The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Jiuxing Liu, Dan E. Poff, Bülent Abali Evaluating high performance communication: a power perspective. Search on Bibsonomy ICS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF iwarp, networking, power, energy, infiniband, rdma
34Mahmut T. Kandemir, Seung Woo Son 0001, Mustafa Karaköy Improving disk reuse for reducing power consumption. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF low power, compiler, disk
34Noureddine Chabini, Wayne H. Wolf Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula Temperature and Process Variations Aware Power Gating of Functional Units. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Shoaib Kamil, John Shalf, Erich Strohmaier Power efficiency in high performance computing. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster Reducing power while increasing performance with supercisc. Search on Bibsonomy ACM Trans. Embedded Comput. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Low-power, synthesis, VLIW, predication, multicore architectures
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