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Searching for phrase sequential circuits (changed automatically) with no syntactic query expansion in all metadata.

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1959-1965 (16) 1966-1968 (19) 1969-1971 (25) 1972-1974 (16) 1975-1980 (15) 1981-1988 (20) 1989-1990 (33) 1991 (33) 1992 (34) 1993 (50) 1994 (41) 1995 (93) 1996 (66) 1997 (72) 1998 (59) 1999 (65) 2000 (61) 2001 (41) 2002 (48) 2003 (48) 2004 (46) 2005 (31) 2006 (30) 2007 (38) 2008 (31) 2009 (22) 2010 (28) 2011-2012 (18) 2013-2014 (21) 2015-2016 (18) 2017 (15) 2018-2019 (13)
Publication types (Num. hits)
article(420) inproceedings(743) phdthesis(3)
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Found 1166 publication records. Showing 1166 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
89Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez Diagnostic of path and gate delay faults in non-scan sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults
82Hideo Fujiwara A New Class of Sequential Circuits with Combinational Test Generation Complexity. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
77Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler Deriving Signal Constraints to Accelerate Sequential Test Generation. Search on Bibsonomy VLSI Design The full citation details ... 1997 DBLP  DOI  BibTeX  RDF sequential test generation algorithm acceleration, signal constraints, large sequential circuits, deterministic sequential test generation, signal constraint computation technique, line probabilities, line justification techniques, benchmark sequential circuits, test generation time reduction, production sequential circuits, 3-valued signal probabilities, fault diagnosis, fault coverage, symbolic simulation, truth table
75Hideo Fujiwara A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
75Debesh K. Das, Bhargab B. Bhattacharya Testable design of non-scan sequential circuits using extra logic. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
67Samir Lejmi, Bozena Kaminska, Bechir Ayari Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudo-exhaustive testing
66Shiyi Xu, Gercy P. Dias Testability forecasting for sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms
63Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya Isomorph-redundancy in sequential circuits. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF isomorph-redundancy, reduced sequential machine, infinite family, VLSI, logic testing, redundancy, integrated circuit testing, design for testability, logic design, sequential circuits, sequential circuits, DFT, state diagram
63Jason P. Hurst, Nick Kanopoulos Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
63Hiroshi Date, Michinobu Nakao, Kazumi Hatayama A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF parallel sequential test generation system, DESCARTES, real-valued logic simulation, redundant fault identification program, algorithmic test generation program, ISCAS '89 benchmark sequential circuits, distributed processing environment oriented system, concurrent accelerative test generation, parallel algorithms, computational complexity, VLSI, fault diagnosis, logic testing, redundancy, design for testability, sequential circuits, logic CAD, VLSI design, stuck-at faults, automatic test generation, synchronous sequential circuits, automatic test software, test quality
62Michiko Inoue, Emil Gizdarski, Hideo Fujiwara A class of sequential circuits with combinational test generation complexity under single-fault assumption. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuck-at-faults, multiple stuck-at faults, single-fault
62Rajesh Nair, Dong Sam Ha VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF parallel pattern fault simulator, VLSI, VLSI, fault diagnosis, heuristics, logic testing, integrated circuit testing, sequential circuits, digital simulation, VISION, circuit analysis computing, flip-flops, synchronous sequential circuits, benchmark circuits
62Yuan Lu, Irith Pomeranz Synchronization of large sequential circuits by partial reset. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF large synchronous sequential circuits, synchronization, sequential circuits, synchronisation, feedback loops, synchronizing sequence, partial reset
59Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal Functional test generation for non-scan sequential circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF nonscan sequential circuits, functional test vectors, growth and disappearance fault model, complete stuck fault coverage, algebraic transformations, synthesized FSMs, VLSI, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, automatic testing, functional test generation
59Stanley Habib, Quan Xu Technology mapping algorithms for sequential circuits using look-up table based FPGAS. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table
59Albrecht P. Stroele Signature analysis and aliasing for sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF built-in self-test techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, built-in self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths
59Srimat T. Chakradhar Optimum retiming of large sequential circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
56Víctor H. Champac, Joan Figueras Testability of floating gate defects in sequential circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flip-flops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flip-flops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing
55Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy Fsimac: a fault simulator for asynchronous sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
55Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita Test sequence compaction for sequential circuits with reset states. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
55Michele Favalli, Cecilia Metra Low-level error recovery mechanism for self-checking sequential circuits. Search on Bibsonomy DFT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF low-level error recovery mechanism, self-checking sequential circuits, reliability requirements, small embedded systems, sequential circuits, design methodology, transient faults, delay faults, fault tolerant capabilities, crosstalk faults
54Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus Improving topological ATPG with symbolic techniques. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF topological ATPG, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, network topology, automatic testing, fault coverage, binary decision diagrams, CPU time, critical areas, symbolic techniques
53Toshiyuki Maeda, Kozo Kinoshita Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
52Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas Statistical path delay fault coverage estimation for synchronous sequential circuits. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
52Jalal A. Wehbeh, Daniel G. Saab Initialization of sequential circuits and its application to ATPG. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF initialization sequence, X-value simulation, functional initializability, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, ATPG, automatic testing, integrated logic circuits, structural decomposition
52O. A. Petlin, Stephen B. Furber Scan testing of asynchronous sequential circuits. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
52Hao Zheng, Kewal K. Saluja, Rajiv Jain Test application time reduction for scan based sequential circuits. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time
52S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault Test configurations to enhance the testability of sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
51Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
50Sujit Dey, Srimat T. Chakradhar Design of testable sequential circuits by repositioning flip-flops. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF cycle-breaking, flip-flop minimization, sequential redundancy, design for testability, sequential circuits, retiming, partial scan, strongly connected components, redundant fault
48Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya Isomorph-Redundancy in Sequential Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF testing, redundancy, ATPG, DFT, stuck-at faults, sequential machines
47Huy Nguyen 0001, Rabindra K. Roy, Abhijit Chatterjee Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1999 DBLP  DOI  BibTeX  RDF sequential circuit BIST, built0in self-test, fault propagation analysis, BIST, partial reset
47Kent L. Einspahr, Sharad C. Seth A switch-level test generation system for synchronous and asynchronous circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF reverse time processing, stuck-open and stuck-at faults, time-frame expansion, sequential circuits, Automatic test generation
47Debesh Kumar Das, Bhargab B. Bhattacharya Does retiming affect redundancy in sequential circuits? Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF combinational redundancy, sequential redundancy, fault diagnosis, logic testing, timing, redundancy, test generation, design for testability, sequential circuits, sequential circuit, fault, retiming, logic optimization, operation speed
46Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal Compaction-based test generation using state and fault information. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation
46Frank F. Hsu, Janak H. Patel A distance reduction approach to design for testability. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flip-flops, flip-flops, synthesis for testability, test function, average distance, DFT techniques
46Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen Verifying sequential equivalence using ATPG techniques. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
45Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara Sequential Test Generation Based on Circuit Pseudo-Transformation. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF acyclic structure, circuit pseudo-transformations, test generation, Sequential circuits, balanced structure
45Fidel Muradali, Janusz Rajski A self-driven test structure for pseudorandom testing of non-scan sequential circuits. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF self-driven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuck-at fault coverage, ISCAS-89 benchmarks, logic testing, built-in self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test
45Mohamed Soufi, Yvon Savaria, F. Darlay, Bozena Kaminska Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1995 DBLP  DOI  BibTeX  RDF full reset, initialization of sequential circuits, modelization of sequential circuits, Markov chain processes, Built-in self-testing, pseudorandom testing, testability measures, partial reset
45Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita Resynthesis for sequential circuits designed with a specified initial state. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF specified initial state, retiming method, redundancy removal method, resynthesized circuit, input sequences, logic optimisation, timing, redundancy, sequential circuits, logic CAD, flip-flops, flip-flops, circuit optimisation, synchronous sequential circuits
45Irith Pomeranz, Sudhakar M. Reddy Classification of Faults in Synchronous Sequential Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF undetectable faults, initial conditions, partially detectable faults, synchronization mode, free mode, logic testing, sequential circuits, synchronisation, fault location, synchronous sequential circuits, combinatorial circuits, test sequence, faults classification, redundant faults
45Hi-Keung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli Test generation for sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
44Kwang-Ting Cheng Transition fault testing for sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
44Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
43Shiyi Xu, Peter Waignjo, Percy G. Dias, Bole Shi Testability Prediction for Sequential Circuits Using Neural Network. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
43Irith Pomeranz, Sudhakar M. Reddy On Test Compaction Objectives for Combinational and Sequential Circuits. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF combinational circuits synchronous sequential circuits test compaction tester storage schemes tester memory requirements
43Jaan Raik, Raimund Ubar Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Search on Bibsonomy J. Electronic Testing The full citation details ... 2000 DBLP  DOI  BibTeX  RDF hierarchical test pattern generation, sequential circuits, register-transfer level, decision diagrams
43Irith Pomeranz, Sudhakar M. Reddy Fault diagnosis based on parameters of output responses. Search on Bibsonomy PRDC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF output responses parameters, unmodeled faults, fault diagnosis, fault diagnosis, logic testing, sequential circuits, dictionaries, synchronous sequential circuits, diagnostic resolution
43Shiyi Xu, Wei Cen Forecasting the efficiency of test generation algorithms for digital circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms
43Steven Parkes, Prithviraj Banerjee, Janak H. Patel A parallel algorithm for fault simulation based on PROOFS . Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
42Irith Pomeranz, Sudhakar M. Reddy Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF built-in test generation, synchronous sequential circuits, at-speed testing
42Shung-Chih Chen, Jer-Min Jou Diagnostic fault simulation for synchronous sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
41Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith 0001, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir Debugging sequential circuits using Boolean satisfiability. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Chia Yee Ooi, Hideo Fujiwara Classification of Sequential Circuits Based on ?k Notation. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith 0001 Debugging Sequential Circuits Using Boolean Satisfiability. Search on Bibsonomy MTV The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Srimat T. Chakradhar, Anand Raghunathan Bottleneck removal algorithm for dynamic compaction in sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
41Chao-Yang Yeh, Malgorzata Marek-Sadowska Delay budgeting in sequential circuit with application on FPGA placement. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF delay budgeting, FPGA, placement, sequential circuits
41Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF synchronizable finite state machines, sequential circuits synthesis, extended synchronizing sequence, scan inputs, normal inputs, MCNC'91 benchmark FSM, minimum-length extended synchronizing sequence, test generation, finite state machines, DFT, heuristic algorithm, minimization, partial scan, synthesis for testability, state assignment, state transition, state encoding
40Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray Deterministic Built-in Pattern Generation for Sequential Circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Comma coding, pattern decoding, statistical encoding, BIST, Huffman coding, run-length encoding, embedded-core testing, sequential circuit testing
40Chen-Pin Kung, Chen-Shang Lin Parallel sequence fault simulation for synchronous sequential circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1996 DBLP  DOI  BibTeX  RDF parallel sequence simulation, fault simulation, logic simulation
40Loganathan Lingappan, Niraj K. Jha Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Chao-Yang Yeh, Malgorzata Marek-Sadowska Minimum-Area Sequential Budgeting for FPGA. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy MIX: A Test Generation System for Synchronous Sequential Circuits. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF deterministic test generation genetic optimization based test generation restricted multiple observation time approach state based test generation synchronous sequential circuits
40Wu-Tung Cheng, Meng-Lin Yu Differential fault simulation for sequential circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1990 DBLP  DOI  BibTeX  RDF test generation, sequential circuits, fault simulation
39Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli Functional clock schedule optimization. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF clock schedule optimization, time frames, level-sensitive sequential circuits, scheduling, delays, delays, timing, sequential circuits, flip-flops, clocks, circuit optimisation, latches, false paths
39Tapan J. Chakraborty, Vishwani D. Agrawal Robust testing for stuck-at faults. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF logic circuit testing, d-robust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuck-at faults, circuit models
39Dimitrios Karayiannis, Spyros Tragoudas Uniform area timing-driven circuit implementation. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF circuit module, cell library, input-output paths, overall area, timing-driven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NP-hard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay
39Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva A portable ATPG tool for parallel and distributed systems. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF portable ATPG tool, memory critical problems, electronic CAD, code portability, PVM library, DEC Alpha AXP, genetic algorithms, genetic algorithm, distributed systems, parallel architectures, parallel architectures, logic testing, message passing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, logic CAD, parallel systems, software portability, message-passing libraries, CM-5
39Bapiraju Vinnakota, Nicholas J. Stessman Reducing test application time in scan design schemes. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF scan design schemes, computationally intractable problem, test vector correlation, graph theory, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic testing, fault simulation, fault coverage, correlation methods, boundary scan testing, test times, test application time, heuristic techniques
39Mohamed Soufi, Yvon Savaria, Bozena Kaminska On the design of at-speed testable VLSI circuits. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
39Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF sequential circuits, Dynamic Bayesian networks, TDM
39Irith Pomeranz, Sudhakar M. Reddy Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF synchronous sequential circuits, test application time, Static test compaction
39Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Test Segment, Parallel Pattern Simulator, Vector Restoration, Single Fault Restoration, Fault Coverage, Synchronous Sequential Circuits, Test Length, Static Test Compaction
39Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel Diagnostic Simulation of Sequential Circuits Using Fault Sampling. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Diagnostic fault simulation, Sampling, Diagnosis, Sequential circuits
39Irith Pomeranz, Sudhakar M. Reddy Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF synchronization, design-for-testability, synchronous sequential circuits
39Koji Yamazaki, Teruhiko Yamada An approach to diagnose logical faults in partially observable sequential circuits. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF logical faults, partially observable sequential circuits, internal nets, error sources, error propagation traceback, failing primary outputs, ISCAS'89 benchmark circuits, fault diagnosis, simulation results, probing, diagnostic resolution
39Martin Keim, Bernd Becker 0001, Birgitta Stenner On the (non-)resetability of synchronous sequential circuits. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF nonresetability, OBDD algorithm, three-valued based greedy algorithm, design, sequential circuits, synchronisation, heuristic algorithm, synchronous sequential circuit, synchronizing sequence, memory elements, resetability
39Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs Dynamic diagnosis of sequential circuits based on stuck-at faults. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF dynamic diagnosis, stuck-at fault simulation, cause-effect analysis, effect-cause analysis, error propagation back-trace, fault diagnosis, logic testing, sequential circuits, synchronous sequential circuit, matching algorithm
38Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja Combinational automatic test pattern generation for acyclic sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. Search on Bibsonomy IWDC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38Peichen Pan, Arvind K. Karandikar, C. L. Liu 0001 Optimal clock period clustering for sequential circuits with retiming. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38Douglas Chang, Malgorzata Marek-Sadowska Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. Search on Bibsonomy FPGA The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
38Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal Functional test generation for synchronous sequential circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
38Soo Young Lee, Kewal K. Saluja Test application time reduction for sequential circuits with scan. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
37Soumitra Bose, Vishwani D. Agrawal Sequential logic path delay test generation by symbolic analysis. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
37Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs Identification of unsettable flip-flops for partial scan and faster ATPG. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF ISCAS89 circuits, deterministic test generation, difficult-to-set hip-hops, hip-hops, state elements, state justification, transformed circuits, unsettable flip-flops identification, logic testing, ATPG, partial scan, sequential circuits test generation
36Dhruva R. Chakrabarti, Ajai Jain An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
36Irith Pomeranz, Sudhakar M. Reddy On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance
36Hiroyuki Higuchi An implication-based method to detect multi-cycle paths in large sequential circuits. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF multi-cycle path, sequential circuits, ATPG, implication
36Irith Pomeranz, Sudhakar M. Reddy On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fault diagnosis, synchronous sequential circuits, synchronizing sequences
36Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF static test compaction synchronous sequential circuits
36Peter A. Krauss, Andreas Ganz, Kurt Antreich Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits. Search on Bibsonomy J. Electronic Testing The full citation details ... 1997 DBLP  DOI  BibTeX  RDF fault parallelism, search space parallelism, sequential circuits, ATPG
36Irith Pomeranz, Sudhakar M. Reddy EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF EXTEST, test generation procedure, logic testing, fault coverage, synchronous sequential circuits, test sequences
36Irith Pomeranz, Sudhakar M. Reddy Built-in test generation for synchronous sequential circuits. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF comparison units, built-in self-test, synchronous sequential circuits, at-speed test
35Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin Power estimation methods for sequential logic circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
35Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen Single-fault fault-collapsing analysis in sequential logic circuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
35Min-Lun Chuang, Chun-Yao Wang Synthesis of reversible sequential elements. Search on Bibsonomy JETC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF sequential elements, sequential circuits, Reversible logic
34Ramesh C. Tekumalla, Premachandran R. Menon Identification of primitive faults in combinational and sequentialcircuits. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid Sequential Circuits for Relational Analysis. Search on Bibsonomy ICSE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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