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Found 1166 publication records. Showing 1166 according to the selection in the facets
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Authors 
Title 
Venue 
Year 
Link 
Author keywords 
89  Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez 
Diagnostic of path and gate delay faults in nonscan sequential circuits. 
VTS 
1995 
DBLP DOI BibTeX RDF 
nonscan sequential circuits, selfmasking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults 
82  Hideo Fujiwara 
A New Class of Sequential Circuits with Combinational Test Generation Complexity. 
IEEE Trans. Computers 
2000 
DBLP DOI BibTeX RDF 
complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure 
77  Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler 
Deriving Signal Constraints to Accelerate Sequential Test Generation. 
VLSI Design 
1997 
DBLP DOI BibTeX RDF 
sequential test generation algorithm acceleration, signal constraints, large sequential circuits, deterministic sequential test generation, signal constraint computation technique, line probabilities, line justification techniques, benchmark sequential circuits, test generation time reduction, production sequential circuits, 3valued signal probabilities, fault diagnosis, fault coverage, symbolic simulation, truth table 
75  Hideo Fujiwara 
A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. 
VLSI Design 
2000 
DBLP DOI BibTeX RDF 
complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure 
75  Debesh K. Das, Bhargab B. Bhattacharya 
Testable design of nonscan sequential circuits using extra logic. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
nonscan sequential circuits, sequentially redundant faults, multiple stuckatfault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design 
67  Samir Lejmi, Bozena Kaminska, Bechir Ayari 
Retiming, resynthesis, and partitioning for the pseudoexhaustive testing of sequential circuits. 
VTS 
1995 
DBLP DOI BibTeX RDF 
segmentation cells, segmentation edges, logic testing, partitioning, timing, sequential circuits, sequential circuits, iterative methods, circuit analysis computing, retiming, iterative algorithm, circuit optimisation, logic partitioning, logic optimization, resynthesis, synchronous circuits, pseudoexhaustive testing 
66  Shiyi Xu, Gercy P. Dias 
Testability forecasting for sequential circuits. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
testability forecasting, transitive closure algorithm, number of test patterns, computational complexity, fault diagnosis, logic testing, logic testing, statistical analysis, design for testability, sequential circuits, sequential circuits, logic CAD, fault coverage, regression models, automatic test software, CPU time, test generation algorithms 
63  Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya 
Isomorphredundancy in sequential circuits. 
VTS 
1996 
DBLP DOI BibTeX RDF 
isomorphredundancy, reduced sequential machine, infinite family, VLSI, logic testing, redundancy, integrated circuit testing, design for testability, logic design, sequential circuits, sequential circuits, DFT, state diagram 
63  Jason P. Hurst, Nick Kanopoulos 
Flipflop sharing in standard scan path to enhance delay fault testing of sequential circuits. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
flipflop sharing, standard scan path, standard scan path design, twovector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flipflops, integrated logic circuits, sequential machines, delay fault testing 
63  Hiroshi Date, Michinobu Nakao, Kazumi Hatayama 
A parallel sequential test generation system DESCARTES based on realvalued logic simulation. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
parallel sequential test generation system, DESCARTES, realvalued logic simulation, redundant fault identification program, algorithmic test generation program, ISCAS '89 benchmark sequential circuits, distributed processing environment oriented system, concurrent accelerative test generation, parallel algorithms, computational complexity, VLSI, fault diagnosis, logic testing, redundancy, design for testability, sequential circuits, logic CAD, VLSI design, stuckat faults, automatic test generation, synchronous sequential circuits, automatic test software, test quality 
62  Michiko Inoue, Emil Gizdarski, Hideo Fujiwara 
A class of sequential circuits with combinational test generation complexity under singlefault assumption. 
Asian Test Symposium 
2000 
DBLP DOI BibTeX RDF 
combinational test generation complexity, internally balanced structures, combinational test generation, separable primary inputs, undetectability, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic test pattern generation, combinational circuits, test sequence, single stuckatfaults, multiple stuckat faults, singlefault 
62  Rajesh Nair, Dong Sam Ha 
VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits. 
VTS 
1995 
DBLP DOI BibTeX RDF 
parallel pattern fault simulator, VLSI, VLSI, fault diagnosis, heuristics, logic testing, integrated circuit testing, sequential circuits, digital simulation, VISION, circuit analysis computing, flipflops, synchronous sequential circuits, benchmark circuits 
62  Yuan Lu, Irith Pomeranz 
Synchronization of large sequential circuits by partial reset. 
VTS 
1996 
DBLP DOI BibTeX RDF 
large synchronous sequential circuits, synchronization, sequential circuits, synchronisation, feedback loops, synchronizing sequence, partial reset 
59  MandyamKomar Srinivas, James Jacob, Vishwani D. Agrawal 
Functional test generation for nonscan sequential circuits. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
nonscan sequential circuits, functional test vectors, growth and disappearance fault model, complete stuck fault coverage, algebraic transformations, synthesized FSMs, VLSI, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, automatic testing, functional test generation 
59  Stanley Habib, Quan Xu 
Technology mapping algorithms for sequential circuits using lookup table based FPGAS. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flipflops, flipflops, circuit layout CAD, table lookup, time delay, lookup table 
59  Albrecht P. Stroele 
Signature analysis and aliasing for sequential circuits. 
VTS 
1995 
DBLP DOI BibTeX RDF 
builtin selftest techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, builtin self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths 
59  Srimat T. Chakradhar 
Optimum retiming of large sequential circuits. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flipflops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation 
56  Víctor H. Champac, Joan Figueras 
Testability of floating gate defects in sequential circuits. 
VTS 
1995 
DBLP DOI BibTeX RDF 
floating gate defect testability, logic detectability conditions, defective transistors, logically untestable branches, scan path cell, CMOS latch cell, scan path flipflops, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, simulated results, flipflops, CMOS logic circuits, integrated circuit modelling, I/sub DDQ/ testing 
55  Susmita SurKolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy 
Fsimac: a fault simulator for asynchronous sequential circuits. 
Asian Test Symposium 
2000 
DBLP DOI BibTeX RDF 
Fsimac, gatelevel fault simulator, Muller Celements, complex domino gates, highspeed design, minmax timing analysis, minmax rime stamps, CABIST, waveform model, logic testing, builtin self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuckat faults, iterations, delay faults, combinational logic, feedback loops, pseudorandom tests, gatedelay faults, asynchronous sequential circuits 
55  Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita 
Test sequence compaction for sequential circuits with reset states. 
Asian Test Symposium 
2000 
DBLP DOI BibTeX RDF 
reset states, test compaction method, single stuckat fault assumption, unremovable vectors, faultdropping fault simulation, nonfaultdropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction 
55  Michele Favalli, Cecilia Metra 
Lowlevel error recovery mechanism for selfchecking sequential circuits. 
DFT 
1997 
DBLP DOI BibTeX RDF 
lowlevel error recovery mechanism, selfchecking sequential circuits, reliability requirements, small embedded systems, sequential circuits, design methodology, transient faults, delay faults, fault tolerant capabilities, crosstalk faults 
54  Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus 
Improving topological ATPG with symbolic techniques. 
VTS 
1995 
DBLP DOI BibTeX RDF 
topological ATPG, fault diagnosis, logic testing, integrated circuit testing, sequential circuits, sequential circuits, network topology, automatic testing, fault coverage, binary decision diagrams, CPU time, critical areas, symbolic techniques 
53  Toshiyuki Maeda, Kozo Kinoshita 
Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults. 
Asian Test Symposium 
2000 
DBLP DOI BibTeX RDF 
I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction 
52  Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, MandyamKomar Srinivas 
Statistical path delay fault coverage estimation for synchronous sequential circuits. 
VLSI Design 
1996 
DBLP DOI BibTeX RDF 
path delay fault coverage estimation, multivalued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation 
52  Jalal A. Wehbeh, Daniel G. Saab 
Initialization of sequential circuits and its application to ATPG. 
VTS 
1996 
DBLP DOI BibTeX RDF 
initialization sequence, Xvalue simulation, functional initializability, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, ATPG, automatic testing, integrated logic circuits, structural decomposition 
52  O. A. Petlin, Stephen B. Furber 
Scan testing of asynchronous sequential circuits. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuckat faults, asynchronous sequential logic, asynchronous sequential circuits 
52  Hao Zheng, Kewal K. Saluja, Rajiv Jain 
Test application time reduction for scan based sequential circuits. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
scan based sequential circuits, single clock configuration, nonscan flipflops, test vector length, nonatomic twoclock scan method, test generation environment, logic testing, sequential circuits, flipflops, clocks, partial scan, boundary scan testing, test application time 
52  S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault 
Test configurations to enhance the testability of sequential circuits. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
shift operation, scan register, test operation, modified flipflops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flipflops, minimisation, scan designs, test application time, test vector 
51  Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara 
MaxTestable Class of Sequential Circuits having Combinational Test Generation Complexity. 
Asian Test Symposium 
2004 
DBLP DOI BibTeX RDF 

50  Sujit Dey, Srimat T. Chakradhar 
Design of testable sequential circuits by repositioning flipflops. 
J. Electronic Testing 
1995 
DBLP DOI BibTeX RDF 
cyclebreaking, flipflop minimization, sequential redundancy, design for testability, sequential circuits, retiming, partial scan, strongly connected components, redundant fault 
48  Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya 
IsomorphRedundancy in Sequential Circuits. 
IEEE Trans. Computers 
2000 
DBLP DOI BibTeX RDF 
testing, redundancy, ATPG, DFT, stuckat faults, sequential machines 
47  Huy Nguyen 0001, Rabindra K. Roy, Abhijit Chatterjee 
Partial Reset Methodology and Experiments for Improving RandomPattern Testability and BIST of Sequential Circuits. 
J. Electronic Testing 
1999 
DBLP DOI BibTeX RDF 
sequential circuit BIST, built0in selftest, fault propagation analysis, BIST, partial reset 
47  Kent L. Einspahr, Sharad C. Seth 
A switchlevel test generation system for synchronous and asynchronous circuits. 
J. Electronic Testing 
1995 
DBLP DOI BibTeX RDF 
reverse time processing, stuckopen and stuckat faults, timeframe expansion, sequential circuits, Automatic test generation 
47  Debesh Kumar Das, Bhargab B. Bhattacharya 
Does retiming affect redundancy in sequential circuits? 
VLSI Design 
1996 
DBLP DOI BibTeX RDF 
combinational redundancy, sequential redundancy, fault diagnosis, logic testing, timing, redundancy, test generation, design for testability, sequential circuits, sequential circuit, fault, retiming, logic optimization, operation speed 
46  Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal 
Compactionbased test generation using state and fault information. 
Asian Test Symposium 
2000 
DBLP DOI BibTeX RDF 
compactionbased test generation, newlytraversed state information, newlydetected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation 
46  Frank F. Hsu, Janak H. Patel 
A distance reduction approach to design for testability. 
VTS 
1995 
DBLP DOI BibTeX RDF 
distance reduction approach, center state, test function embedding technique, SFT techniques, logic testing, finite state machines, finite state machines, design for testability, design for testability, sequential circuits, sequential circuits, flipflops, flipflops, synthesis for testability, test function, average distance, DFT techniques 
46  ShiYu Huang, KwangTing Cheng, KuangChien Chen 
Verifying sequential equivalence using ATPG techniques. 
ACM Trans. Design Autom. Electr. Syst. 
2001 
DBLP DOI BibTeX RDF 

45  Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara 
Sequential Test Generation Based on Circuit PseudoTransformation. 
Asian Test Symposium 
1997 
DBLP DOI BibTeX RDF 
acyclic structure, circuit pseudotransformations, test generation, Sequential circuits, balanced structure 
45  Fidel Muradali, Janusz Rajski 
A selfdriven test structure for pseudorandom testing of nonscan sequential circuits. 
VTS 
1996 
DBLP DOI BibTeX RDF 
selfdriven test structure, primary inputs, nonscan sequential circuits, test point structure, parallel pseudorandom test patterns, test mode flag, stuckat fault coverage, ISCAS89 benchmarks, logic testing, builtin self test, integrated circuit testing, design for testability, sequential circuits, BIST, automatic testing, circuit under test 
45  Mohamed Soufi, Yvon Savaria, F. Darlay, Bozena Kaminska 
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors. 
IEEE Trans. Computers 
1995 
DBLP DOI BibTeX RDF 
full reset, initialization of sequential circuits, modelization of sequential circuits, Markov chain processes, Builtin selftesting, pseudorandom testing, testability measures, partial reset 
45  Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita 
Resynthesis for sequential circuits designed with a specified initial state. 
VTS 
1995 
DBLP DOI BibTeX RDF 
specified initial state, retiming method, redundancy removal method, resynthesized circuit, input sequences, logic optimisation, timing, redundancy, sequential circuits, logic CAD, flipflops, flipflops, circuit optimisation, synchronous sequential circuits 
45  Irith Pomeranz, Sudhakar M. Reddy 
Classification of Faults in Synchronous Sequential Circuits. 
IEEE Trans. Computers 
1993 
DBLP DOI BibTeX RDF 
undetectable faults, initial conditions, partially detectable faults, synchronization mode, free mode, logic testing, sequential circuits, synchronisation, fault location, synchronous sequential circuits, combinatorial circuits, test sequence, faults classification, redundant faults 
45  HiKeung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. SangiovanniVincentelli 
Test generation for sequential circuits. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
1988 
DBLP DOI BibTeX RDF 

44  KwangTing Cheng 
Transition fault testing for sequential circuits. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
1993 
DBLP DOI BibTeX RDF 

44  Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici 
SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
1991 
DBLP DOI BibTeX RDF 

43  Shiyi Xu, Peter Waignjo, Percy G. Dias, Bole Shi 
Testability Prediction for Sequential Circuits Using Neural Network. 
Asian Test Symposium 
1997 
DBLP DOI BibTeX RDF 

43  Irith Pomeranz, Sudhakar M. Reddy 
On Test Compaction Objectives for Combinational and Sequential Circuits. 
VLSI Design 
1998 
DBLP DOI BibTeX RDF 
combinational circuits synchronous sequential circuits test compaction tester storage schemes tester memory requirements 
43  Jaan Raik, Raimund Ubar 
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. 
J. Electronic Testing 
2000 
DBLP DOI BibTeX RDF 
hierarchical test pattern generation, sequential circuits, registertransfer level, decision diagrams 
43  Irith Pomeranz, Sudhakar M. Reddy 
Fault diagnosis based on parameters of output responses. 
PRDC 
2000 
DBLP DOI BibTeX RDF 
output responses parameters, unmodeled faults, fault diagnosis, fault diagnosis, logic testing, sequential circuits, dictionaries, synchronous sequential circuits, diagnostic resolution 
43  Shiyi Xu, Wei Cen 
Forecasting the efficiency of test generation algorithms for digital circuits. 
Asian Test Symposium 
2000 
DBLP DOI BibTeX RDF 
efficiency forecasting, testability parameters, genetic algorithms, genetic algorithms, VLSI, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic test pattern generation, ATPG, combinational circuits, combinational circuits, digital circuits, VLSI circuits, digital integrated circuits, test generation algorithms 
43  Steven Parkes, Prithviraj Banerjee, Janak H. Patel 
A parallel algorithm for fault simulation based on PROOFS . 
ICCD 
1995 
DBLP DOI BibTeX RDF 
fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning 
42  Irith Pomeranz, Sudhakar M. Reddy 
BuiltIn Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. 
IEEE Trans. Computers 
2002 
DBLP DOI BibTeX RDF 
builtin test generation, synchronous sequential circuits, atspeed testing 
42  ShungChih Chen, JerMin Jou 
Diagnostic fault simulation for synchronous sequential circuits. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
1997 
DBLP DOI BibTeX RDF 

41  Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith 0001, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir 
Debugging sequential circuits using Boolean satisfiability. 
ICCAD 
2004 
DBLP DOI BibTeX RDF 

41  Chia Yee Ooi, Hideo Fujiwara 
Classification of Sequential Circuits Based on ?k Notation. 
Asian Test Symposium 
2004 
DBLP DOI BibTeX RDF 

41  Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith 0001 
Debugging Sequential Circuits Using Boolean Satisfiability. 
MTV 
2004 
DBLP DOI BibTeX RDF 

41  Srimat T. Chakradhar, Anand Raghunathan 
Bottleneck removal algorithm for dynamic compaction in sequential circuits. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
1997 
DBLP DOI BibTeX RDF 

41  ChaoYang Yeh, Malgorzata MarekSadowska 
Delay budgeting in sequential circuit with application on FPGA placement. 
DAC 
2003 
DBLP DOI BibTeX RDF 
delay budgeting, FPGA, placement, sequential circuits 
41  Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara 
An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. 
Asian Test Symposium 
1996 
DBLP DOI BibTeX RDF 
synchronizable finite state machines, sequential circuits synthesis, extended synchronizing sequence, scan inputs, normal inputs, MCNC'91 benchmark FSM, minimumlength extended synchronizing sequence, test generation, finite state machines, DFT, heuristic algorithm, minimization, partial scan, synthesis for testability, state assignment, state transition, state encoding 
40  Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray 
Deterministic Builtin Pattern Generation for Sequential Circuits. 
J. Electronic Testing 
1999 
DBLP DOI BibTeX RDF 
Comma coding, pattern decoding, statistical encoding, BIST, Huffman coding, runlength encoding, embeddedcore testing, sequential circuit testing 
40  ChenPin Kung, ChenShang Lin 
Parallel sequence fault simulation for synchronous sequential circuits. 
J. Electronic Testing 
1996 
DBLP DOI BibTeX RDF 
parallel sequence simulation, fault simulation, logic simulation 
40  Loganathan Lingappan, Niraj K. Jha 
Improving the Performance of Automatic Sequential Test Generation by Targeting HardtoTest Faults. 
VLSI Design 
2006 
DBLP DOI BibTeX RDF 

40  ChaoYang Yeh, Malgorzata MarekSadowska 
MinimumArea Sequential Budgeting for FPGA. 
ICCAD 
2003 
DBLP DOI BibTeX RDF 

40  Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy 
MIX: A Test Generation System for Synchronous Sequential Circuits. 
VLSI Design 
1998 
DBLP DOI BibTeX RDF 
deterministic test generation genetic optimization based test generation restricted multiple observation time approach state based test generation synchronous sequential circuits 
40  WuTung Cheng, MengLin Yu 
Differential fault simulation for sequential circuits. 
J. Electronic Testing 
1990 
DBLP DOI BibTeX RDF 
test generation, sequential circuits, fault simulation 
39  Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. SangiovanniVincentelli 
Functional clock schedule optimization. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
clock schedule optimization, time frames, levelsensitive sequential circuits, scheduling, delays, delays, timing, sequential circuits, flipflops, clocks, circuit optimisation, latches, false paths 
39  Tapan J. Chakraborty, Vishwani D. Agrawal 
Robust testing for stuckat faults. 
VLSI Design 
1995 
DBLP DOI BibTeX RDF 
logic circuit testing, drobust tests, fault diagnosis, logic testing, delays, sequential circuits, sequential circuits, fault models, combinational circuits, combinational circuit, robust testing, single stuckat faults, circuit models 
39  Dimitrios Karayiannis, Spyros Tragoudas 
Uniform area timingdriven circuit implementation. 
Great Lakes Symposium on VLSI 
1995 
DBLP DOI BibTeX RDF 
circuit module, cell library, inputoutput paths, overall area, timingdriven circuit implementation, computational complexity, heuristics, CAD, delays, timing, sequential circuits, sequential circuits, NPhard, directed graphs, combinational circuits, combinational circuits, logic CAD, polynomial time algorithm, directed acyclic graphs, circuit CAD, cellular arrays, propagation delay 
39  Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva 
A portable ATPG tool for parallel and distributed systems. 
VTS 
1995 
DBLP DOI BibTeX RDF 
portable ATPG tool, memory critical problems, electronic CAD, code portability, PVM library, DEC Alpha AXP, genetic algorithms, genetic algorithm, distributed systems, parallel architectures, parallel architectures, logic testing, message passing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, logic CAD, parallel systems, software portability, messagepassing libraries, CM5 
39  Bapiraju Vinnakota, Nicholas J. Stessman 
Reducing test application time in scan design schemes. 
VTS 
1995 
DBLP DOI BibTeX RDF 
scan design schemes, computationally intractable problem, test vector correlation, graph theory, fault diagnosis, logic testing, sequential circuits, sequential circuits, automatic testing, fault simulation, fault coverage, correlation methods, boundary scan testing, test times, test application time, heuristic techniques 
39  Mohamed Soufi, Yvon Savaria, Bozena Kaminska 
On the design of atspeed testable VLSI circuits. 
VTS 
1995 
DBLP DOI BibTeX RDF 
atspeed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuckat test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, designfortestability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique 
39  Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan 
A stimulusfree graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. 
ACM Trans. Design Autom. Electr. Syst. 
2006 
DBLP DOI BibTeX RDF 
sequential circuits, Dynamic Bayesian networks, TDM 
39  Irith Pomeranz, Sudhakar M. Reddy 
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. 
IEEE Trans. Computers 
2000 
DBLP DOI BibTeX RDF 
synchronous sequential circuits, test application time, Static test compaction 
39  Xijiang Lin, WuTung Cheng, Irith Pomeranz, Sudhakar M. Reddy 
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. 
VTS 
2000 
DBLP DOI BibTeX RDF 
Test Segment, Parallel Pattern Simulator, Vector Restoration, Single Fault Restoration, Fault Coverage, Synchronous Sequential Circuits, Test Length, Static Test Compaction 
39  Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel 
Diagnostic Simulation of Sequential Circuits Using Fault Sampling. 
VLSI Design 
1998 
DBLP DOI BibTeX RDF 
Diagnostic fault simulation, Sampling, Diagnosis, Sequential circuits 
39  Irith Pomeranz, Sudhakar M. Reddy 
DesignforTestability for Synchronous Sequential Circuits using Locally Available Lines. 
DATE 
1998 
DBLP DOI BibTeX RDF 
synchronization, designfortestability, synchronous sequential circuits 
39  Koji Yamazaki, Teruhiko Yamada 
An approach to diagnose logical faults in partially observable sequential circuits. 
Asian Test Symposium 
1997 
DBLP DOI BibTeX RDF 
logical faults, partially observable sequential circuits, internal nets, error sources, error propagation traceback, failing primary outputs, ISCAS'89 benchmark circuits, fault diagnosis, simulation results, probing, diagnostic resolution 
39  Martin Keim, Bernd Becker 0001, Birgitta Stenner 
On the (non)resetability of synchronous sequential circuits. 
VTS 
1996 
DBLP DOI BibTeX RDF 
nonresetability, OBDD algorithm, threevalued based greedy algorithm, design, sequential circuits, synchronisation, heuristic algorithm, synchronous sequential circuit, synchronizing sequence, memory elements, resetability 
39  Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs 
Dynamic diagnosis of sequential circuits based on stuckat faults. 
VTS 
1996 
DBLP DOI BibTeX RDF 
dynamic diagnosis, stuckat fault simulation, causeeffect analysis, effectcause analysis, error propagation backtrace, fault diagnosis, logic testing, sequential circuits, synchronous sequential circuit, matching algorithm 
38  Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja 
Combinational automatic test pattern generation for acyclic sequential circuits. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
2005 
DBLP DOI BibTeX RDF 

38  Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu 
Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded CoresBased Sequential Circuits. 
IWDC 
2004 
DBLP DOI BibTeX RDF 

38  Peichen Pan, Arvind K. Karandikar, C. L. Liu 0001 
Optimal clock period clustering for sequential circuits with retiming. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
1998 
DBLP DOI BibTeX RDF 

38  Douglas Chang, Malgorzata MarekSadowska 
Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. 
FPGA 
1998 
DBLP DOI BibTeX RDF 

38  MandyamKomar Srinivas, James Jacob, Vishwani D. Agrawal 
Functional test generation for synchronous sequential circuits. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
1996 
DBLP DOI BibTeX RDF 

38  Soo Young Lee, Kewal K. Saluja 
Test application time reduction for sequential circuits with scan. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
1995 
DBLP DOI BibTeX RDF 

37  Soumitra Bose, Vishwani D. Agrawal 
Sequential logic path delay test generation by symbolic analysis. 
Asian Test Symposium 
1995 
DBLP DOI BibTeX RDF 
sequential logic path delay test generation, twovector test sequences, nonscan sequential circuit, multivalued algebras, threevector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions 
37  Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs 
Identification of unsettable flipflops for partial scan and faster ATPG. 
ICCAD 
1996 
DBLP DOI BibTeX RDF 
ISCAS89 circuits, deterministic test generation, difficulttoset hiphops, hiphops, state elements, state justification, transformed circuits, unsettable flipflops identification, logic testing, ATPG, partial scan, sequential circuits test generation 
36  Dhruva R. Chakrabarti, Ajai Jain 
An Efficient Test Generation Technique for Sequential Circuits with Repetitive SubCircuits. 
VLSI Design 
1996 
DBLP DOI BibTeX RDF 

36  Irith Pomeranz, Sudhakar M. Reddy 
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. 
IEEE Trans. Computers 
2006 
DBLP DOI BibTeX RDF 
overtesting, test generation, Designfortestability, synchronous sequential circuits, redundant faults, fullscan, fault dominance 
36  Hiroyuki Higuchi 
An implicationbased method to detect multicycle paths in large sequential circuits. 
DAC 
2002 
DBLP DOI BibTeX RDF 
multicycle path, sequential circuits, ATPG, implication 
36  Irith Pomeranz, Sudhakar M. Reddy 
On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. 
VLSI Design 
2000 
DBLP DOI BibTeX RDF 
fault diagnosis, synchronous sequential circuits, synchronizing sequences 
36  Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy 
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. 
DATE 
1998 
DBLP DOI BibTeX RDF 
static test compaction synchronous sequential circuits 
36  Peter A. Krauss, Andreas Ganz, Kurt Antreich 
Distributed Test Pattern Generation for StuckAt Faults in Sequential Circuits. 
J. Electronic Testing 
1997 
DBLP DOI BibTeX RDF 
fault parallelism, search space parallelism, sequential circuits, ATPG 
36  Irith Pomeranz, Sudhakar M. Reddy 
EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. 
VTS 
1997 
DBLP DOI BibTeX RDF 
EXTEST, test generation procedure, logic testing, fault coverage, synchronous sequential circuits, test sequences 
36  Irith Pomeranz, Sudhakar M. Reddy 
Builtin test generation for synchronous sequential circuits. 
ICCAD 
1997 
DBLP DOI BibTeX RDF 
comparison units, builtin selftest, synchronous sequential circuits, atspeed test 
35  ChiYing Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin 
Power estimation methods for sequential logic circuits. 
IEEE Trans. VLSI Syst. 
1995 
DBLP DOI BibTeX RDF 

35  Jwu E. Chen, ChungLen Lee, WenZen Shen 
Singlefault faultcollapsing analysis in sequential logic circuits. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
1991 
DBLP DOI BibTeX RDF 

35  MinLun Chuang, ChunYao Wang 
Synthesis of reversible sequential elements. 
JETC 
2008 
DBLP DOI BibTeX RDF 
sequential elements, sequential circuits, Reversible logic 
34  Ramesh C. Tekumalla, Premachandran R. Menon 
Identification of primitive faults in combinational and sequentialcircuits. 
IEEE Trans. on CAD of Integrated Circuits and Systems 
2001 
DBLP DOI BibTeX RDF 

34  Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid 
Sequential Circuits for Relational Analysis. 
ICSE 
2007 
DBLP DOI BibTeX RDF 

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