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Publications at "IEEE Trans. VLSI Syst."( http://dblp.L3S.de/Venues/IEEE_Trans._VLSI_Syst. )

URL (DBLP): http://dblp.uni-trier.de/db/journals/tvlsi

Publication years (Num. hits)
1993 (59) 1994 (54) 1995 (48) 1996 (46) 1997 (48) 1998 (82) 1999 (56) 2000 (85) 2001 (97) 2002 (98) 2003 (114) 2004 (137) 2005 (140) 2006 (135) 2007 (141) 2008 (176) 2009 (177) 2010 (190) 2011 (240) 2012 (242) 2013 (240) 2014 (273) 2015 (335) 2016 (344) 2017 (333) 2018 (274) 2019 (258)
Publication types (Num. hits)
article(4422)
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Found 4422 publication records. Showing 4422 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Eberle A. Rambo, Yunsheng Shang, Rolf Ernst Providing Integrity in Real-Time Networks-on-Chip. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Gyuseong Kang, Jongsun Park 0001 Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yuqi Wang, Amira Aouina, Hui Li 0034, Ian O'Connor, Gabriela Nicolescu, Sébastien Le Beux Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jihye Kim, Sangjun Lee, Sungho Kang Test-Friendly Data-Selectable Self-Gating (DSSG). Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Pan Xue, Yilei Shen, Dan Fang, Chenyang Wang, Haijun Shao, Ting Yi, Xiaoyang Zeng, Zhiliang Hong A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jing Guo 0004, Shanshan Liu, Lei Zhu 0004, Fabrizio Lombardi A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Cheng-En Hsieh, Shen-Iuan Liu A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Dae-Hyun Kim, Shu-Han Hsu, Linda Milor Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ing-Chao Lin, Da-Wei Chang, Chen-Tai Kao, Sheng-Xuan Lin Infection-Based Dead Page Prediction in Hybrid Memory Architecture. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Daiguo Xu, Hequan Jiang, Lei Qiu 0002, Xiaoquan Yu, Jianan Wang, Zhengping Zhang, Can Zhu, Shiliu Xu A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Scott Lerner, Baris Taskin Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sadegh Yazdanshenas, Vaughn Betz The Costs of Confidentiality in Virtualized FPGAs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kouki Mohamed Model Order Reduction Method for Large-Scale RC Interconnect and Implementation of Adaptive Digital PI Controller. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas Four-Level Forms for Memristive Material Implication Logic. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Luong N. Nguyen, Chia-Lin Cheng, Milos Prvulovic, Alenka G. Zajic Creating a Backscattering Side Channel to Enable Detection of Dormant Hardware Trojans. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Albert Ciprut, Eby G. Friedman Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Junyoung Ko, Younghwi Yang, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim, Seong-Ook Jung Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki An Analog LO Harmonic Suppression Technique for SDR Receivers. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Xinyi Ge, Yong Chen 0005, Xiaoteng Zhao, Pui-In Mak, Rui P. Martins Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Congyi Zhu, Renrong Liang, Jun Lin, Zhongfeng Wang, Li Li Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yu-Kai Chiu, Shen-Iuan Liu A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Amard Afzalian, Hossein Miar Naimi, Massoud Dousti What Is the Maximum Achievable Oscillation Frequency in a Specified CMOS Process? Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jiann-Jong Chen, Yuh-Shyan Hwang, Jun-Yi Lin, Yi-Tsen Ku A Dead-Beat-Controlled Fast-Transient-Response Buck Converter With Active Pseudo-Current-Sensing Techniques. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Scott Lerner, Isikcan Yilmaz, Baris Taskin Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Tao-Chun Yu, An-Jie Shih, Shao-Yun Fang Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yanping Gong, Fengyu Qian, Lei Wang 0003 Design for Test and Hardware Security Utilizing Retention Loss of Memristors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Christian Pilato, Kanad Basu, Francesco Regazzoni, Ramesh Karri Black-Hat High-Level Synthesis: Myth or Reality? Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Yao Xiao, Shahin Nazarian, Paul Bogdan Self-Optimizing and Self-Programming Computing Systems: A Combined Compiler, Complex Networks, and Machine Learning Approach. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kwangmin Kim, Seokjoon Kang, Byungsub Kim A Code Inversion Encoding Technique to Improve Read Margin of A Cross-Point Phase Change Memory. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Abdulqader Mahmoud, Mohammad Alhawari, Baker Mohammad, Hani H. Saleh, Mohammed Ismail 0001 A Gain-Controlled, Low-Leakage Dickson Charge Pump for Energy-Harvesting Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Sara Choi, Hong Keun Ahn, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Myeongjin Kim, Wontaeck Jung, Hyukjun Lee, Eui-Young Chung A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Takao Oshita, Jonathan Douglas, Arun Krishnamoorthy High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Haomiao Wang, Prabu Thiagaraj, Oliver Sinnen Harmonic-Summing Module of SKA on FPGA - Optimizing the Irregular Memory Accesses. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Manas Kumar Lenka, Gaurab Banerjee A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Pavan Kumar Javvaji, Spyros Tragoudas On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hang Wang, Tiancheng Wang, Longjun Liu, Hongbin Sun 0001, Nanning Zheng Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Hayoung Lee, Donghyun Han, Seungtaek Lee, Sungho Kang Dynamic Built-In Redundancy Analysis for Memory Repair. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Jackson Melchert, Setareh Behroozi, Jingjie Li, Younghyun Kim SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Donkyu Baek, Naehyuck Chang Runtime Power Management of Battery Electric Vehicles for Extended Range With Consideration of Driving Time. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Shao-I Chu, Chen-En Hsieh, Yu-Jung Huang Design of FSM-Based Function With Reduced Number of States in Integral Stochastic Computing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Florian Zaruba, Luca Benini The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han 0001, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu 0001, Wei Zhang 0012, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ned Bingham, Rajit Manohar Self-Timed Adaptive Digit-Serial Addition. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Olivier Muller, Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot Efficient Decompression of Binary Encoded Balanced Ternary Sequences. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Pedro Reviriego, Anees Ullah, Salvatore Pontarelli PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev A Parametric DFT Scheme for STT-MRAMs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Mehrnaz Ahmadi, Sahand Salamat, Bijan Alizadeh A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Song-Nien Tang, Fu-Chiang Jan Energy-Efficient and Calibration-Aware Fourier-Domain OCT Imaging Processor. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ben Perach, Shahar Kvatinsky An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
1Ata Khorami, Mohammad Sharifkhani A Low-Power High-Speed Comparator for Precise Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yung-Hui Chung, Chia-Wei Yen, Pei-Kang Tsai, Bo-Wei Chen A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Sravan K. Marella, Sachin S. Sapatnekar Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung H. Kang, Yuan Xie 0001 An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Chung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Alec Roelke, Mircea R. Stan Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Adwaya Kulkarni, Adam Page, Nasrin Attaran, Ali Jafari, Maria Malik, Houman Homayoun, Tinoosh Mohsenin An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi Automatic Correction of Dynamic Power Management Architecture in Modern Processors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Sabri Unsal, Adrián Cristal, Mateo Valero Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Cuiping Shao, Huiyun Li Identifying Single-Event Transient Location Based on Compressed Sensing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Divya Pathak, Ioannis Savidis On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Daniel O'Hare, Anthony G. Scanlan, Eric Thompson, Brendan Mullane Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mehdi Safarpour, Reza Inanlou, Mostafa Charmi, Omid Shoaei, Olli Silvén ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Huyen Thi Pham, Hanho Lee Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Xuan Dong 0003, Lihong Zhang Analog Layout Retargeting With Process-Variation-Aware Hybrid OPC. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Donghyun Kim, Hayoung Lee, Sungho Kang An Area-Efficient BIRA With 1-D Spare Segments. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Masoud Pashaeifar, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shuo-Han Chen, Yen-Ting Chen, Yuan-Hao Chang, Hsin-Wen Wei, Wei-Kuan Shih A Progressive Performance Boosting Strategy for 3-D Charge-Trap NAND Flash. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Md Tanvir Arafin, Gang Qu Memristors for Secret Sharing-Based Lightweight Authentication. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Tahmid Abtahi, Colin Shea, Amey M. Kulkarni, Tinoosh Mohsenin Accelerating Convolutional Neural Network With FFT on Embedded Hardware. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Miki Tanaka, Shinji Shinji, Koji Nii A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Davide Giri, Giovanni Causapruno, Fabrizio Riente Parallel and Serial Computation in Nanomagnet Logic: An Overview. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mohammad Torabi, Lihong Zhang Electromigration- and Parasitic-Aware ILP-Based Analog Router. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Srivatsa Rangachar Srinivasa, Xueqing Li, Meng-Fan Chang, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Peeyoosh Mirajkar, Jagdish Chand Goyal, Sankaran Aniruddhan, Srinivas Theertham Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Irith Pomeranz Observation Points on State Variables for the Compaction of Multicycle Tests. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Costas Argyrides, Jie Li Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Shanker Shreejith, Libin K. Mathew, A. Prasad Vinod, Suhaib A. Fahmy Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yizhi Wang, Jun Lin, Zhongfeng Wang An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yun Long, Taesik Na, Saibal Mukhopadhyay ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Yonghong Tao, Andreas Hierlemann A 15-Channel 30-V Neural Stimulator for Spinal Cord Repair. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Aiwen Luo, Fengwei An, Xiangyu Zhang 0002, Lei Chen 0001, Hans Jürgen Mattausch Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Nahid Mirzaie, Ahmed Alzahmi, Hossein Shamsi, Gyung-Su Byun Three-Dimensional Pipeline ADC Utilizing TSV/ Design Optimization and Memristor Ratioed Logic. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Alok Prakash, Christopher T. Clarke, Siew-Kei Lam, Thambipillai Srikanthan Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Xin Cai, Mingda Zhou, Tian Xia, Wai H. Fong, Wing-Tsz Lee, Xinming Huang 0001 Low-Power SDR Design on an FPGA for Intersatellite Communications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Vasileios Leon, Georgios Zervakis, Dimitrios Soudris, Kiamal Z. Pekmestzi Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Mohammad Fardad, Sayed Masoud Sayedi, Ehsan Yazdian Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
1Dongliang Chen, Jonathon Edstrom, Yifu Gong, Peng Gao, Lei Yang, Mark E. McCourt, Jinhui Wang, Na Gong Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
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