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Publications at "IEEE Trans. VLSI Syst."( http://dblp.L3S.de/Venues/IEEE_Trans._VLSI_Syst. )

URL (DBLP): http://dblp.uni-trier.de/db/journals/tvlsi

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1993 (59) 1994 (54) 1995 (48) 1996 (46) 1997 (48) 1998 (82) 1999 (56) 2000 (85) 2001 (97) 2002 (98) 2003 (114) 2004 (137) 2005 (140) 2006 (135) 2007 (141) 2008 (176) 2009 (177) 2010 (190) 2011 (240) 2012 (242) 2013 (240) 2014 (273) 2015 (335) 2016 (344) 2017 (333) 2018 (274) 2019 (258)
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article(4422)
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Found 4422 publication records. Showing 4422 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Zhonghai Lu, Yuan Yao Dynamic Traffic Regulation in NoC-Based Systems. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Guanghui Hu, Jin Sha, Zhongfeng Wang High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ramtin Zand, Arman Roohi, Ronald F. DeMara Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Daniel Kraak, Mottaqiallah Taouil, Innocent Agbo, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chun-Hsing Li, Chun-Lin Ko, Ming-Ching Kuo, Da-Chiang Chang A 7.1-mW K/Ka-Band Mixer With Configurable Bondwire Resonators in 65-nm CMOS. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Mohammad Ali Montazerolghaem, Tohid Moosazadeh, Mohammad Yavari A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Reza Zendegani, Mehdi Kamal, Milad Bahadori, Ali Afzali-Kusha, Massoud Pedram RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat Self-Controlled High-Performance Precharge-Free Content-Addressable Memory. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Alejandro Valero, Negar Miralaei, Salvador Petit, Julio Sahuquillo, Timothy M. Jones 0001 On Microarchitectural Mechanisms for Cache Wearout Reduction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yelim Youn, Kwangmin Kim, Jae-Yoon Sim, Hong-June Park, Byungsub Kim Investigation on the Worst Read Scenario of a ReRAM Crossbar Array. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Mahmoud Meribout, Samir Teniou A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Menglong Guan, Lei Wang 0003 Improving DRAM Performance in 3-D ICs via Temperature Aware Refresh. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Xiang Zhang 0007, Liter Siek An 80.4% Peak Power Efficiency Adaptive Supply Class H Power Amplifier for Audio Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yung-Hui Chung, Chia-Wei Yen An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Siyuan Xu, Benjamin Carrión Schäfer Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Sheis Abolma'ali, Nika Mansouri-Ghiasi, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Amir M. Rahmani, Mohammad Hashem Haghbayan, Antonio Miele, Pasi Liljeberg, Axel Jantsch, Hannu Tenhunen Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez Logic Design Partitioning for Stacked Power Domains. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Babak Zamanlooy, Mitra Mirhassani An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zhe Yuan, Yongpan Liu, Jinyang Li 0002, Jingtong Hu, Chun Jason Xue, Huazhong Yang CP-FPGA: Energy-Efficient Nonvolatile FPGA With Offline/Online Checkpointing Optimization. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hiromitsu Awano, Shumpei Morita, Takashi Sato Scalable Device Array for Statistical Characterization of BTI-Related Parameters. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Qing Liu 0005, Wei Shu, Joseph S. Chang A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chio-In Ieong, Mingzhong Li, Man-Kay Law, Pui-In Mak, Mang I Vai, Rui Paulo Martins A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Marta Ortín-Obón, Mahdi Tala, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Raviteja P. Reddy, Amit Acharyya, S. Saqib Khursheed A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Mohammed Zackriya V, Harish M. Kittur Content Addressable Memory - Early Predict and Terminate Precharge of Match-Line. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Dina M. Ellaithy, Magdy A. El-Moursy, Ghada H. Ibrahim, Amal Zaki, Abdelhalim Zekry Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chen Hou, Qianchuan Zhao Stopping-Time Management of Smart Sensing Nodes Based on Tradeoffs Between Accuracy and Power Consumption. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Xiaoliang Dai, Niraj K. Jha Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Soonyoung Cha, Taizhi Liu, Linda Milor Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shalini Pathak, Anuj Grover, Mausumi Pohit, Nitin Bansal LoCCo-Based Scan Chain Stitching for Low-Power DFT. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ahmed Awad 0002, Atsushi Takahashi 0001, Satoshi Tanaka, Chikaaki Kodama A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Dwaipayan Biswas, Koushik Maharatna, Goran Panic, Evangelos B. Mazomenos, Josy Achner, Jasmin Klemke, Michael Jöbges, Steffen Ortmann Low-Complexity Framework for Movement Classification Using Body-Worn Sensors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Muhammad Sanaullah, Masud H. Chowdhury Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Mario Garrido, Miguel Angel Sánchez, María Luisa López Vallejo, Jesús Grajal A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Younghyun Lim, Jeonghyun Lee, Yongsun Lee, Seong-Sik Song, Hong-Teuk Kim, Ockgoo Lee, Jaehyouk Choi An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Robert Giterman, Lior Atias, Adam Teman Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1J. M. Mora-Gutiérrez, C. J. Jiménez-Fernández, M. Valencia-Barrero Multiradix Trivium Implementations for Low-Power IoT Hardware. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Gyuseong Kang, Woong Choi, Jongsun Park 0001 Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zhenqiang Yong, Xiaoyan Xiang, Chen Chen, Jianyi Meng An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Immanuel Raja, Vishal Khatri, Zaira Zahir, Gaurab Banerjee A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jinn-Shyan Wang, Shih-Nung Wei Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti Approximate Error Detection With Stochastic Checkers. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Doron Gluzer, Shmuel Wimer Probability-Driven Multibit Flip-Flop Integration With Clock Gating. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yu Liu, Yier Jin, Aria Nosratinia, Yiorgos Makris Silicon Demonstration of Hardware Trojan Design and Detection in Wireless Cryptographic ICs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Mohammad Taherzadeh-Sani, Said M. Hussain Hussaini, Hamidreza Rezaee-Dehsorkh, Frederic Nabki, Mohamad Sawan A 170-dB Ω CMOS TIA With 52-pA Input-Referred Noise and 1-MHz Bandwidth for Very Low Current Sensing. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hesheng Lin, Wing Chun Chan, Wai Kwong Lee, Zhirong Chen, Mansun Chan, Min Zhang High-Current Drivability Fibonacci Charge Pump With Connect-Point-Shift Enhancement. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chien-Chung Ho, Yu-Ping Liu, Yuan-Hao Chang, Tei-Wei Kuo Antiwear Leveling Design for SSDs With Hybrid ECC Capability. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Xiaoliang Dai, Niraj K. Jha Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Martin Omaña, Daniele Rossi 0001, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Mohammad Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu 0001, Wei Zhang 0012, Zhengya Zhang, Stacey Weber Jackson Editorial. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hailang Wang, Emre Salman Closed-Form Expressions for I/O Simultaneous Switching Noise Revisited. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Wenchao Qian, Christopher Babecki, Robert Karam, Somnath Paul, Swarup Bhunia ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yongyuan Li, Zhangming Zhu A 30-W 90% Efficiency Dual-Mode Controlled DC-DC Controller With Power Over Ethernet Interface for Power Device. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jie Guo 0002, Danghui Wang, Zili Shao, Yiran Chen Data-Pattern-Aware Error Prevention Technique to Improve System Reliability. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Amit Kazimirsky, Adam Teman, Noa Edri, Alexander Fish A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Pil-Ho Lee, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zhiheng Wang 0002, Ryan N. Goh, Kia Bazargan, Arnd Scheel, Naman Saraf Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Nishit Ashok Kapadia, Sudeep Pasricha A Runtime Framework for Robust Application Scheduling With Adaptive Parallelism in the Dark-Silicon Era. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Bhagyaraja Adapa, Dwaipayan Biswas, Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya, Koushik Maharatna Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jiaji He, Yiqiang Zhao, Xiaolong Guo, Yier Jin Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel Statistical Analysis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Michael Cheah, Debashis Mandal, Bertan Bakkaloglu, Sayfe Kiaei A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ahmad A. Hiasat A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n-1, 2n+1, 22n+1, 22n+p}. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yang Xu 0005, Xinwang Zhang, Zhihua Wang, Baoyong Chi A Flexible Continuous-Time Δ Σ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hsiang-Jen Tsai, Keng-Hao Yang, Yin-Chi Peng, Chien-Chen Lin, Ya-Han Tsao, Meng-Fan Chang, Tien-Fu Chen Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Fahim Rahman, Bicky Shakya, Xiaolin Xu, Domenic Forte, Mark Tehranipoor Security Beyond CMOS: Fundamentals, Applications, and Roadmap. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hao-Ting Shen, Fahim Rahman, Bicky Shakya, Xiaolin Xu, Mark Tehranipoor, Domenic Forte Poly-Si-Based Physical Unclonable Functions. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Ahmad T. Sheikh, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Sadiq M. Sait A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Taeyoung Kim 0001, Zeyu Sun, Hai-Bao Chen, Hai Wang 0002, Sheldon X.-D. Tan Energy and Lifetime Optimizations for Dark Silicon Manycore Microprocessor Considering Both Hard and Soft Errors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Wen Yuan, Jeffrey S. Walling A Switched-Capacitor-Controlled Digital-Current Modulated Class-E Transmitter. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Manjari Pradhan, Bhargab B. Bhattacharya COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Seyed Alireza Zahrai, Marina Zlochisti, Nicolas Le Dortz, Marvin Onabajo A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hyeonggyu Kim, Soontae Kim, Jooheung Lee Write-Amount-Aware Management Policies for STT-RAM Caches. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee 0001, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada Embedded Deterministic Test Points. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zia Uddin Ahamed Khan, Mohammed Benaissa High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas Delay Analysis for Current Mode Threshold Logic Gate Designs. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Dong Wang 0006, Xiao Liang Tan, Pak Kwong Chan A 65-nm CMOS Constant Current Source With Reduced PVT Variation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Srikar Bhagavatula, Byunghoo Jung Variation Resilient Power Sensor With an 80-ns Response Time for Fine-Grained Power Management. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Divya Pathak, Houman Homayoun, Ioannis Savidis Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Yizhi Zhao, Xuecheng Zou, Zhaojun Lu, Zhenglin Liu Chaotic Encrypted Polar Coding Scheme for General Wiretap Channel. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Xue Liu 0003, Xin-Xin Yan, Ze-ke Wang, Qingxu Deng Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1S. Rasool Hosseini, Mehdi Saberi, Reza Lotfi A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Shraddha Bodhe, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim In-DRAM Data Initialization. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Enyi Yao, Arindam Basu VLSI Extreme Learning Machine: A Design Space Exploration. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Xiang Feng, Shuguo Li Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Xiangyu Li, Chaoqun Yang, Jiangsha Ma, Yongchang Liu, Shujuan Yin Energy-Efficient Side-Channel Attack Countermeasure With Awareness and Hybrid Configuration Based on It. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Woo-Rham Bae, Borivoje Nikolic, Deog-Kyoon Jeong Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Weize Yu, Selçuk Köse Security-Adaptive Voltage Conversion as a Lightweight Countermeasure Against LPA Attacks. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Farshad Firouzi, Bahar Farahani, Andrew B. Kahng, Jan M. Rabaey, Natasha Balac Guest Editorial: Alternative Computing and Machine Learning for Internet of Things. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Fernando Garcia-Redondo, Pablo Royer, Marisa López-Vallejo, Hernan Aparicio, Pablo Ituero, Carlos A. López-Barrio Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
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