Search results for "1080p"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
72	Nan Wu 0003, Mei Wen, Wei Wu, Ju Ren 0002, Huayou Su, Changqing Xun, Chunyuan Zhang	Streaming HD H.264 encoder on programmable processors.	ACM Multimedia	2009	DBLP DOI BibTeX RDF	1080P HD, H.264 encoder, real-time, stream, programmable
51	Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang	A 242mW, 10mm21080p H.264/AVC high profile encoder chip.	DAC	2008	DBLP DOI BibTeX RDF	1080p, high profile, encoder, H.264
41	Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin	FPGA Prototyping Strategy for a H.264/AVC Video Decoder.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
31	Ju Ren 0002, Mei Wen, Chunyuan Zhang, Huayou Su, Yi He 0008, Nan Wu 0003	A Parallel Streaming Motion Estimation for Real-Time HD H.264 Encoding on Programmable Processors.	FCST	2010	DBLP DOI BibTeX RDF	HD H.264/AVC, 1080p, parallel programming, motion estimation, GPU, stream processing
28	Tun-Hao Yang, Tian-Sheuan Chang	ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator With Decoupled Asymmetric Convolution.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
28	Ties van Rozendaal, Tushar Singhal, Hoang Le, Guillaume Sautière, Amir Said, Krishna Buska, Anjuman Raha, Dimitris Kalatzis, Hitarth Mehta, Frank Mayer, Liang Zhang, Markus Nagel, Auke Wiggers	MobileNVC: Real-time 1080p Neural Video Compression on a Mobile Device.	WACV	2024	DBLP DOI BibTeX RDF
28	Tun-Hao Yang, Tian-Sheuan Chang	ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator with Decoupled Asymmetric Convolution.	CoRR	2023	DBLP DOI BibTeX RDF
28	Ties van Rozendaal, Tushar Singhal, Hoang Le, Guillaume Sautière, Amir Said, Krishna Buska, Anjuman Raha, Dimitris Kalatzis, Hitarth Mehta, Frank Mayer, Liang Zhang, Markus Nagel, Auke Wiggers	MobileNVC: Real-time 1080p Neural Video Compression on a Mobile Device.	CoRR	2023	DBLP DOI BibTeX RDF
28	Feng Min, Haobo Xu, Ying Wang 0001, Yujie Wang, Jiajun Li, Xingqi Zou, Bei Li, Yinhe Han 0001	Dadu-Eye: A 5.3 TOPS/W, 30 fps/1080p High Accuracy Stereo Vision Accelerator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
28	Dragomir M. El Mezeni, Lazar Saranovac	Fast guided filter for power-efficient real-time 1080p streaming video processing.	J. Real Time Image Process.	2020	DBLP DOI BibTeX RDF
28	Xuchong Zhang, Hongbin Sun 0001, Shiqiang Chen, Nanning Zheng 0001	VLSI Architecture Exploration of Guided Image Filtering for 1080P@60Hz Video Processing.	IEEE Trans. Circuits Syst. Video Technol.	2018	DBLP DOI BibTeX RDF
28	Gustavo Sanchez, Ramon Fernandes, Rodrigo Cataldo, Luciano Agostini, César A. M. Marcon	Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p Videos.	ICECS	2018	DBLP DOI BibTeX RDF
28	Gustavo Sanchez, Luciano Volcan Agostini, César A. M. Marcon	High Efficient Architecture for 3D-HEVC DMM-1 Decoder Targeting 1080p Videos.	ISCAS	2018	DBLP DOI BibTeX RDF
28	Chun-Ting Yen, Wan-Yu Chen, Liang-Gee Chen	A 120 fps 1080p resolution block-based feature extraction architecture implementation for real-time action recognition.	ISCAS	2017	DBLP DOI BibTeX RDF
28	Wenping Zhu, Leibo Liu, Guangli Jiang, Shouyi Yin, Shaojun Wei	A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator.	IEEE Trans. Circuits Syst. Video Technol.	2016	DBLP DOI BibTeX RDF
28	Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha, Sylvain Hochberg, Patrick Garda	A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
28	Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei	A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space.	CICC	2015	DBLP DOI BibTeX RDF
28	Shuo-Wen Hsu, Tian Sheuan Chang	A real time 1080P 30FPS Gaussian Mixture Modeling design for background subtraction and object extraction.	ICCE-TW	2014	DBLP DOI BibTeX RDF
28	Gustavo Sanchez, Bruno Zatt, Marcelo Schiavon Porto, Luciano Volcan Agostini	A Real-Time 5-Views HD 1080p Architecture for 3D-HEVC Depth Modeling Mode 4.	SBCCI	2014	DBLP DOI BibTeX RDF
28	Mariangela Genovese, Ettore Napoli, Davide De Caro, Nicola Petra, Antonio G. M. Strollo	FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video.	J. Electr. Comput. Eng.	2013	DBLP DOI BibTeX RDF
28	Guoyong Li, Leibo Liu, Shouyi Yin, Changkui Mao, Shaojun Wei	Mapping IDCT of MPEG2 on Coarse-Grained Reconfigurable Array for Matching 1080p Video Decoding.	EMC/HumanCom	2013	DBLP DOI BibTeX RDF
28	Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic	MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping.	ESSCIRC	2013	DBLP DOI BibTeX RDF
28	Kazuyuki Miyazawa, Hiroharu Sakate, Shun-ichi Sekiguchi, Nobuaki Motoyama, Yasuko Sugito, Kazuhisa Iguchi, Atsuro Ichigaya, Shinichi Sakaida	Real-time hardware implementation of HEVC video encoder for 1080p HD video.	PCS	2013	DBLP DOI BibTeX RDF
28	Leibo Liu, Weilong Zhang, Chenchen Deng, Shouyi Yin, Shanshan Cai, Shaojun Wei	SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process.	CICC	2013	DBLP DOI BibTeX RDF
28	Yongha Park, Chang-Hyo Yu, Kilwhan Lee, Hyunsuk Kim, Youngeun Park, Chun-Ho Kim, Yunseok Choi, Jinhong Oh, Changhoon Oh, Gurnrack Moon, Sangduk Kim, Horang Jang, Jin-Aeon Lee, Chinhyun Kim, Sungho Park	72.5GFLOPS 240Mpixel/s 1080p 60fps multi-format video codec application processor enabled with GPGPU for fused multimedia application.	ISSCC	2013	DBLP DOI BibTeX RDF
28	Byung Cheol Song, Yongseok Yi, Yun-Gu Lee, Nak Hoon Kim, Jun Hyuk Ko, Tae Hee Kim, Dong Keun Lim, Woo Hyun Ju, Jae-Pil Moon, Kyunghwan Cho	1080p 60 Hz Intra-Frame Video CODEC Chip Design and Its Implementation.	J. Signal Process. Syst.	2012	DBLP DOI BibTeX RDF
28	Pierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gürkaynak	A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
28	Mariangela Genovese, Ettore Napoli	An FPGA-based Real-time Background Identification Circuit for 1080p Video.	SITIS	2012	DBLP DOI BibTeX RDF
28	Zhibin Xiao, Bevan M. Baas	A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System.	IEEE Trans. Circuits Syst. Video Technol.	2011	DBLP DOI BibTeX RDF
28	Sung-Fang Tsai, Chao-Chung Cheng, Chung-Te Li, Liang-Gee Chen	A real-time 1080p 2D-to-3D video conversion system.	IEEE Trans. Consumer Electron.	2011	DBLP DOI BibTeX RDF
28	Chun-Hsien Huang, Chung-Ling Wu	Image Information Processing System for Hemispherical Screen With Dual 1080P High-Resolution Projectors.	J. Inf. Sci. Eng.	2010	DBLP BibTeX RDF
28	Jimit Shah, K. S. Raghunandan 0001, Kuruvilla Varghese	Area optimized H.264 Intra prediction architecture for 1080p HD resolution.	ASAP	2010	DBLP DOI BibTeX RDF
28	Byung Cheol Song, Yongseok Yi, Yun-Gu Lee, Jun Hyuk Ko, Tae Hee Kim	1080P 60HZ intra-frame CODEC based on RGB color space for wireless AV streaming.	ICIP	2009	DBLP DOI BibTeX RDF
28	Shang-Te Yang, Tsung-Kai Lin, Shao-Yi Chien	Real-time Motion Estimation for 1080p videos on graphics processing units with shared memory optimization.	SiPS	2009	DBLP DOI BibTeX RDF
28	Cláudio Machado Diniz, Bruno Zatt, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi	A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video.	ICME	2009	DBLP DOI BibTeX RDF
28	Yongseok Yi, Byung Cheol Song	High-Speed CAVLC Encoder for 1080p 60-Hz H.264 Codec.	IEEE Signal Process. Lett.	2008	DBLP DOI BibTeX RDF
28	Sumito Arakawa, Yuji Yamaguchi, Satoshi Akui, Yasushi Fukuda, Hirofumi Sumi, Hiroshi Hayashi, Masahiro Igarashi, Kei Ito, Hidetoshi Nagano, Masatoshi Imai, Naosuke Asari	A 512GOPS Fully-Programmable Digital Image Processor with full HD 1080p Processing Capabilities.	ISSCC	2008	DBLP DOI BibTeX RDF
28	Yu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang	A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip.	ISSCC	2008	DBLP DOI BibTeX RDF
21	Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, Sreeramula Sankaraiah, Sravanthi Mantha, S. K. Nandy 0001, Ranjani Narayan	An Input Triggered Polymorphic ASIC for H.264 Decoding.	ASAP	2009	DBLP DOI BibTeX RDF
21	Daniela Kuka, Oliver Elias, Ronald Martins, Christopher Lindinger, Andreas Pramböck, Andreas Jalsovec, Pascal Maresch, Horst Hörtner, Peter Brandl	DEEP SPACE: High Resolution VR Platform for Multi-user Interactive Narratives.	ICIDS	2009	DBLP DOI BibTeX RDF
21	Jeffrey M. Gilbert, Chinh H. Doan, Sohrab Emami, C. Bernard Shung	A 4-Gbps Uncompressed Wireless HD A/V Transceiver Chipset.	IEEE Micro	2008	DBLP DOI BibTeX RDF	uncompressed, HDMI, multimedia, networking, wireless, video, CMOS, high-definition, 60 GHz
21	Raj Amirtharajah, John R. Mashey	Guest Editors' Introduction: Hot Chips 19.	IEEE Micro	2008	DBLP DOI BibTeX RDF	wireless HD, fault tolerance, mobile computing, low-power, GPU, computer architecture, microprocessors, mainframe computing, Hot Chips 19
21	Kermin Fleming, Chun-Chieh Lin, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks	H.264 Decoder: A Case Study in Multiple Design Points.	MEMOCODE	2008	DBLP DOI BibTeX RDF
21	Bruno Zatt, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini	HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Yongseok Yi, Byung Cheol Song	A novel CAVLC architecture for H.264 Video encoding at high bit-rate.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Jiayi Zhu 0001, Peilin Liu, Dajiang Zhou	An SDRAM controller optimized for high definition video coding application.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Yu-Yu Lee, Yu-Hsuan Lee, Tsung-Han Tsai 0001	An efficient lossless embedded compression engine using compacted-FELICS algorithm.	SoCC	2008	DBLP DOI BibTeX RDF
21	Vagner S. Rosa, Altamiro Amadeu Susin, Sergio Bampi	An HDTV H.264 deblocking filter in FPGA with RGB video output.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
21	Zhenyu Liu 0001, Yang Song 0002, Ming Shao, Shen Li, Lingfeng Li, Satoshi Goto, Takeshi Ikenaga	32-Parallel SAD Tree Hardwired Engine for Variable Block Size Motion Estimation in HDTV1080P Real-Time Encoding Application.	SiPS	2007	DBLP DOI BibTeX RDF
21	Ron Brachman	Emerging Sciences of the Internet: Some New Opportunities.	ESWC	2007	DBLP DOI BibTeX RDF
21	Wesley De Neve, Dieter Van Rijsselbergen, Charles-Frederik Hollemeersch	GPU-assisted decoding of video samples represented in the YCoCg-R color space.	ACM Multimedia	2005	DBLP DOI BibTeX RDF	FRExt, YCoCg, YCoCg-R, GPU, H.264/AVC, pixel shaders