Search results for "ANOC"

Found 8 publication records. Showing 8 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
120	Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner	Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture.	NOCS	2008	DBLP DOI BibTeX RDF	DSPIN, ANOC, physical implementation, FAUST, bi-synchronous FIFO, network-on-chip, NoC
37	Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang	High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).	ISCAS	2015	DBLP DOI BibTeX RDF
37	Sylvain Durand, Suzanne Lesecq, Edith Beigné, Diego Puschini	Event-based DVFS control in GALS-ANoC MPSoCs.	ACC	2013	DBLP DOI BibTeX RDF
37	Peng Zhang 0011, Chuang Lin 0002, Yixin Jiang, Patrick P. C. Lee, John C. S. Lui	ANOC: Anonymous Network-Coding-Based Communication with Efficient Cooperation.	IEEE J. Sel. Areas Commun.	2012	DBLP DOI BibTeX RDF
37	Yvain Thonnart, Edith Beigné, Pascal Vivet	Design and Implementation of a GALS Adapter for ANoC Based Architectures.	ASYNC	2009	DBLP DOI BibTeX RDF
37	Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet	Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction.	ASYNC	2008	DBLP DOI BibTeX RDF
28	Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach	A DFT Architecture for Asynchronous Networks-on-Chip.	ETS	2006	DBLP DOI BibTeX RDF
28	Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.	VLSI-SoC	2005	DBLP DOI BibTeX RDF

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