|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 3 occurrences of 3 keywords
|
|
|
Results
Found 2 publication records. Showing 2 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
96 | Didier Demigny, Lounis Kessal, R. Bourguiba, N. Boudouani |
How to Use High Speed Reconfigurable FPGA for Real Time Image Processing? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 240-, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
high speed reconfigurable FPGA, ARDOISE, video frame duration, architectural concepts, partitioning methodology, image segmentation, image segmentation, hardware architecture, real time image processing |
30 | Sophie Bouchoux, El-Bay Bourennane, Johel Mitéran, Michel Paindavoine |
Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 237-238, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #2 of 2 (100 per page; Change: )
|
|