Search results for "Accellera"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Michael J. C. Gordon	Validating the PSL/Sugar Semantics Using Automated Reasoning.	Formal Aspects Comput.	2003	DBLP DOI BibTeX RDF	Accellera, Property language, Sugar, Model checking, Semantics, Formal verification, Theorem proving, Higher-order logic, PSL, HOL
80	Shrenik Mehta	Industry Standards from Accellera.	VLSI Design	2008	DBLP DOI BibTeX RDF
58	Michael J. C. Gordon, Joe Hurd, Konrad Slind	Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving.	CHARME	2003	DBLP DOI BibTeX RDF
36	Gabe Moretti	Accellera's Support for ESL Verification and Stimulus Reuse.	IEEE Des. Test	2017	DBLP DOI BibTeX RDF
36	Gabe Moretti	Accellera's DVCon Conferences Focus on the Community of Practicing Engineers.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
36	John Stickley, Deepak Kumar Garg, Brian Bailey, Jaekwang Lee, Amy Lim, Per Bojsen, Ramesh Chandra, Ajeya Prabhakar	Understanding the Accellera SCE-MI Transaction Pipes.	IEEE Des. Test Comput.	2012	DBLP DOI BibTeX RDF
36	Peter J. Ashenden	Standards: Technical activities in Accellera.	IEEE Des. Test Comput.	2002	DBLP BibTeX RDF
22	Sri Chandra	Driving Analog Mixed Signal Verification through Verilog-AMS.	VLSI Design	2008	DBLP DOI BibTeX RDF
22	John Goodenough 0001	Design Automation Standards: The IP Providers Perspective.	VLSI Design	2008	DBLP DOI BibTeX RDF
22	Keijo Heljanko, Tommi A. Junttila, Misa Keinänen, Martin Lange, Timo Latvala	Bounded Model Checking for Weak Alternating Büchi Automata.	CAV	2006	DBLP DOI BibTeX RDF	Weak Alternating Büchi Automata, Bounded Model Checking, PSL, NuSMV
22	Thomas Tuerk, Klaus Schneider 0001, Mike Gordon	Model Checking PSL Using HOL and SMV.	Haifa Verification Conference	2006	DBLP DOI BibTeX RDF
22	Thomas Tuerk, Klaus Schneider 0001	From PSL to LTL: A Formal Validation in HOL.	TPHOLs	2005	DBLP DOI BibTeX RDF
22	Kausik Datta, Partha Pratim Das	Assertion Based Verification Using HDVL.	VLSI Design	2004	DBLP DOI BibTeX RDF
22	Bijan Alizadeh, Zainalabedin Navabi	Using Integer Equations to Check PSL Properties in RT Level Design.	IWSOC	2004	DBLP DOI BibTeX RDF
22	Daniel Geist	The PSL/Sugar Specification Language A Language for all Seasons.	CHARME	2003	DBLP DOI BibTeX RDF
22	Shuqing Zhao, Daniel Gajski	Modeling a new RTL semantics in C++.	ISCAS (5)	2002	DBLP DOI BibTeX RDF