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Found 12 publication records. Showing 12 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
93 | Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel |
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 210-, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
completion detection, Brent-Kung, Carry-Bypass, asynchronous, adders, hazards, high-performance design |
66 | Zhiyu Liu, Volkan Kursun |
Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1389-1392, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
66 | Zhiyu Liu, Volkan Kursun |
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 239-244, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling |
60 | Matthew M. Ziegler, Mircea R. Stan |
A Unified Design Space for Regular Parallel Prefix Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1386-1387, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Kogge-Stone adder, Han-Carlson adder, Brent-Kung adder, parallel prefix adder |
56 | A. Niyas Ahamed, M. Madheswaran |
Hybrid Brent Kung Adder with Modified Sum Generator for Energy Efficient Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(12), pp. 2350212:1-2350212:14, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
56 | Aruru Sai Kumar, U. Siddhesh, N. Sai Kiran, K. Bhavitha |
Design of High Speed 8-bit Vedic Multiplier using Brent Kung Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 13th International Conference on Computing Communication and Networking Technologies, ICCCNT 2022, Kharagpur, India, October 3-5, 2022, pp. 1-5, 2022, IEEE, 978-1-6654-5262-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
33 | Sabyasachi Das, Sunil P. Khatri |
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(3), pp. 326-331, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Christopher Umans |
Fast polynomial factorization and modular composition in small characteristic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 40th Annual ACM Symposium on Theory of Computing, Victoria, British Columbia, Canada, May 17-20, 2008, pp. 481-490, 2008, ACM, 978-1-60558-047-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
modular composition, multipoint evaluation, polynomial factorization |
33 | Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner |
Variable delay ripple carry adder with carry chain interrupt detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 113-116, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-performance carry chains for FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 138-147, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Scott Hauck, Matthew M. Hosler, Thomas W. Fry |
High-Performance Carry Chains for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 223-233, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Tudor Jebelean |
Systolic Algorithms for Long Integer GCD Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 241-252, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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