Search results for "Cutsize"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
118	Jason Cong, Sung Kyu Lim, Chang Wu	Performance driven multi-level and multiway partitioning with retiming.	DAC	2000	DBLP DOI BibTeX RDF
96	Andrew B. Kahng, Xu Xu 0001	Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
96	Andrew B. Kahng, Xu Xu 0001	Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning.	ISPD	2003	DBLP DOI BibTeX RDF
77	Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis	Multi-objective circuit partitioning for cutsize and path-based delay minimization.	ICCAD	2002	DBLP DOI BibTeX RDF
59	Jason Cong, Chang Wu	Global clustering-based performance-driven circuit partitioning.	ISPD	2002	DBLP DOI BibTeX RDF	clustering, partitioning, performance optimization, retiming, VLSI CAD
59	Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu	Large scale circuit partitioning with loose/stable net removal and signal flow based clustering.	ICCAD	1997	DBLP DOI BibTeX RDF
59	Jason Cong, Wilburt Labio, Narayanan Shivakumar	Multiway VLSI circuit partitioning based on dual net representation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
56	Ling Wang 0004, Henry Selvaraj	Performance Driven Circuit Clustering and Partitioning.	ITCC	2002	DBLP DOI BibTeX RDF	Cutsize, Clustering, Delay, Partitioning
37	Takayuki Nozaki	Cutsize Distributions of Balanced Hypergraph Bipartitions for Random Hypergraphs.	CoRR	2016	DBLP BibTeX RDF
37	Takayuki Nozaki	Cutsize distributions of balanced hypergraph bipartitions for random hypergraphs.	ISIT	2016	DBLP DOI BibTeX RDF
20	Lijun Li, Carl Tropper	A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation.	PADS	2007	DBLP DOI BibTeX RDF
20	Jason Cong, Michail Romesis, Joseph R. Shinnerl	Fast floorplanning by look-ahead enabled recursive bipartitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
20	Jason Cong, Michail Romesis, Joseph R. Shinnerl	Fast floorplanning by look-ahead enabled recursive bipartitioning.	ASP-DAC	2005	DBLP DOI BibTeX RDF
20	Chanseok Hwang, Massoud Pedram	PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits.	ASP-DAC	2005	DBLP DOI BibTeX RDF
20	Jason Cong, Sung Kyu Lim	Edge separability-based circuit clustering with application to multilevel circuit partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
20	Jiyoun Kim, Marios C. Papaefthymiou, Athar B. Tayyab	An Algorithm for Geometric Load Balancing with Two Constraints.	IPDPS	2004	DBLP DOI BibTeX RDF
20	Dongku Kang, Mark C. Johnson, Kaushik Roy 0001	Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan.	ISQED	2004	DBLP DOI BibTeX RDF
20	Jason Cong, Michail Romesis, Min Xie 0004	Optimality, scalability and stability study of partitioning and placement algorithms.	ISPD	2003	DBLP DOI BibTeX RDF	optimality, scalability, stability, partitioning, placement
20	C. K. Eem, J. W. Chong	An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures.	ASP-DAC	1999	DBLP DOI BibTeX RDF
20	Susan Flynn Hummel, Graham D. Riley, Rizos Sakellariou	Scheduling and Load Balancing.	Euro-Par	1998	DBLP DOI BibTeX RDF
20	K. S. Seong, C. M. Kyung	Two-way partitioning based on direction vector [layout design].	ED&TC	1997	DBLP DOI BibTeX RDF
20	Shantanu Dutt, Wenyong Deng	VLSI circuit partitioning by cluster-removal using iterative improvement techniques.	ICCAD	1996	DBLP DOI BibTeX RDF	ACM/SIGDA benchmark circuits, Fiduccia-Mattheyses algorithm, VLSI circuit partitioning, cluster-removal, iterative improvement techniques, look-ahead algorithm, partition quality, spectral partitioner MELO, VLSI, CAD
20	Andrew B. Kahng	Fast Hypergraph Partition.	DAC	1989	DBLP DOI BibTeX RDF