Search results for "DDFS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Sau-Gee Chen, Jen-Chuan Chih, Jun-Yi Chou	Direct Digital Frequency Synthesis Based on a Two-Level Table-Lookup Scheme.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	direct digital frequency synthesizer, DDFS algorithm, two-level table lookup scheme
93	Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin	A Low-Power Efficient Direct Digital Frequency Synthesizer Based on New Two-Level Lookup Table.	CCECE	2006	DBLP DOI BibTeX RDF
84	Shiann Shiun Jeng, Hsing-Chen Lin, Chen-Yu Wu	DDFS design using the equi-section division method for SDR transceiver.	PIMRC	2008	DBLP DOI BibTeX RDF
65	Seng-Pan U., Rui Paulo Martins, José E. Franca	A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
56	Ashkan Ashrafi, Aleksandar Milenkovic, Reza R. Adhami	A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method.	ISCAS	2007	DBLP DOI BibTeX RDF
56	Xuefeng Yu, Foster F. Dai, Yin Shi, Ronghua Zhu	2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
56	Dimitrios Soudris, Marios Kesoulis, Christos S. Koukourlis, Adonios Thanailakis, Spyros Blionas	Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
56	Chang Yong Kang, Earl E. Swartzlander Jr.	An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis.	ASAP	2002	DBLP DOI BibTeX RDF
56	Linda Kwai-Lin Lau, Rajeev Jain, Henry Samueli, Henry T. Nicholas III, Etan G. Cohen	DDFSGEN.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
48	Jun Chen, Rong Luo, Huazhong Yang, Hui Wang 0004	A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator.	VLSI Design	2006	DBLP DOI BibTeX RDF	Direct digital frequency synthesizer (DDFS), preset value phase accumulator (PVPA), ROM-less look up table, low power
48	Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe	Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	DDFS, NCO, direct digital frequency synthesizer, numerically controlled oscillator, phase accumulator, low power
48	J. M. Pierre Langlois, Dhamin Al-Khalili	A low power direct digital frequency synthesizer with 60 dBc spectral purity.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	DDFS, DDS, phase to sine amplitude conversion, low power
37	Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh	A low-power high-SFDR CMOS direct digital frequency synthesizer.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
37	Alistair McEwan, Steve Collins	Analogue interpolation based direct digital frequency synthesis.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
37	Florean Curticapean, K. I. Palomaki, Jarkko Niittylahti	Quadrature direct digital frequency synthesizer using an angle rotation algorithm.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
28	Jae-Yun Park, Su-Hyeon Kim, Hyunyoung Yoo, Jae-Won Nam	Analysis of Quarter Method Applied ROM-Based DDFS Architecture.	IEEE Access	2023	DBLP DOI BibTeX RDF
28	Tzung-Je Lee, Hung-Hsiang Chang, Chien-Hsiang Chao	High Bandwidth Efficiency FPGA-based Underwater Acoustic Transceiver with Adaptive-SFDR DDFS.	ISOCC	2023	DBLP DOI BibTeX RDF
28	Matthew M. Peet	Representation of networks and systems with delay: DDEs, DDFs, ODE-PDEs and PIEs.	Autom.	2021	DBLP DOI BibTeX RDF
28	Chua-Chin Wang, Nanang Sulistiyanto, Hsiang-Yu Shih, Yu-Cheng Lin, Wei Wang	Power-effective ROM-less DDFS Design Approach with High SFDR Performance.	J. Signal Process. Syst.	2020	DBLP DOI BibTeX RDF
28	Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Hsiang-Yu Shih	74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
28	Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa	A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
28	Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa	A 7GS/s Complete-DDFS-Solution in 65nm CMOS.	IEICE Trans. Electron.	2018	DBLP DOI BibTeX RDF
28	Tsung-Yi Tsai, Hsiang-Yu Shih, Chua-Chin Wang	A pipeline ROM-less DDFS using equal-division interpolation.	ISOCC	2017	DBLP DOI BibTeX RDF
28	Wei Wang, Yuan-Yuan Xu, Chua-Chin Wang	Dynamic power estimation for ROM-less DDFS designs using switching activity analysis.	ISOCC	2017	DBLP DOI BibTeX RDF
28	Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa	A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
28	Shiann Shiun Jeng, Hsing-Chen Lin, Wei-Sheng Jhuang, Yen-Ching Lee	A novel low-spur DDFS utilizing the twice second-order high-pass error feedback architecture.	Int. J. Circuit Theory Appl.	2014	DBLP DOI BibTeX RDF
28	Ashkan Ashrafi	Optimization of the Quantized Coefficients for DDFS Utilizing Polynomial Interpolation Methods.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
28	Keerthi S. Asok, Karuna P. Sahoo	Digital hardware optimization for 1.5-GHz high-speed DDFS.	ICECS	2014	DBLP DOI BibTeX RDF
28	Sandeep D'Souza, Frank Hsiao, Adrian Tang 0002, Sai-Wang Tam, Roc Berenguer, Mau-Chung Frank Chang	A 10-Bit 2-GS/s DAC-DDFS-IQ-Controller Baseband Enabling a Self-Healing 60-GHz Radio-on-Chip.	IEEE Trans. Circuits Syst. II Express Briefs	2013	DBLP DOI BibTeX RDF
28	Ashkan Ashrafi	On the SFDR Upperbound in DDFS Utilizing Polynomial Interpolation Methods.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
28	Kanitpong Pengwon, Ekachai Leelarasmee	A Compact Design of a Low Frequency Quadrature DDFS with Low Distortion Using Analog Shapers.	IEICE Trans. Commun.	2011	DBLP DOI BibTeX RDF
28	Chua-Chin Wang, Chia-Hao Hsu, Chia-Chuan Lee, Jian-Ming Huang	A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset.	J. Signal Process. Syst.	2011	DBLP DOI BibTeX RDF
28	Petter Kallstrom, Oscar Gustafsson	Magnitude scaling for increased SFDR in DDFS.	NORCHIP	2011	DBLP DOI BibTeX RDF
28	Carlos Bernal 0001, Pilar Molina-Gaudó, Arturo Mediano	Direct DDFS FM modulator with baseband interpolator.	ISCAS	2010	DBLP DOI BibTeX RDF
28	Luca Marchetti, Luca Iocchi	Reducing Impact of Conflicting Data in DDFS by Using Second Order Knowledge.	SETN	2010	DBLP DOI BibTeX RDF
28	Emanuele Lopelli, Johan van der Tang, Arthur H. M. van Roermund	Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
28	Farhad Babak, Parviz Keshavarzi	A Novel DDFS Based on Trigonometric Approximation with a Scaling Block.	ITNG	2009	DBLP DOI BibTeX RDF	phase to sine-amplitude conversion, quadrant phase, quarter symmetry, spurious free dynamic range (SFDR), compression ratio
28	Hiroomi Hikawa	DDFS with New Sinusoid Approximation based on Harmonics Removal.	ISCAS	2009	DBLP DOI BibTeX RDF
28	Andrea Bonfanti, Davide De Caro, Alfio Dario Grasso, Salvatore Pennisi, Carlo Samori, Antonio G. M. Strollo	A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
28	Adrian Maxim, Ramin Khoini-Poorfard, Mitchell Reid, James T. Kao, Charles D. Thompson, Richard A. Johnson	A DDFS Driven Mixing-DAC with Image and Harmonic Rejection Capabilities.	ISSCC	2008	DBLP DOI BibTeX RDF
28	Chua-Chin Wang, Chia-Hao Hsu, Tuo-Yu Yao, Jian-Ming Huang	A ROM-less DDFS using a nonlinear DAC with an error compensation current array.	APCCAS	2008	DBLP DOI BibTeX RDF
28	Hoon Hee Chung, Umar Lyles, Tino Copani, Bertan Bakkaloglu, Sayfe Kiaei	A Bandpass ΔΣ DDFS-Driven 19GHz Frequency Synthesizer for FMCW Automotive Radar.	ISSCC	2007	DBLP DOI BibTeX RDF
28	Seng-Pan U, Rui Paulo Martins, José E. Franca	A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
28	Ashkan Ashrafi, Reza R. Adhami, Laurie L. Joiner, Parisa Kaveh	Arbitrary waveform DDFS utilizing Chebyshev polynomials interpolation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2004	DBLP DOI BibTeX RDF
28	Michael Chappell, Alistair McEwan	A low power high speed accumulator for DDFS applications.	ISCAS (2)	2004	DBLP BibTeX RDF
28	Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang	1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
28	Heung-Gyoon Ryu, Yun-Young Kim, Hyeong-Man Yu, Hyun-Seok Lee	A new triple-controlled type frequency synthesizer using simplified DDFS-driven digital hybrid PLL system.	IEEE Trans. Consumer Electron.	2002	DBLP DOI BibTeX RDF
28	Heung-Gyoon Ryu, Yun-Young Kim, Hyeong-Man Yu, Sang Burm Ryu	Design of DDFS-driven PLL frequency synthesizer with reduced complexity.	IEEE Trans. Consumer Electron.	2001	DBLP DOI BibTeX RDF
19	Yong-Eun Kim, Su-Hyun Cho, Jin-Gyun Chung	Modified CSD group multiplier design for predetermined coefficient groups.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Heng Tao Shen, Xiaofang Zhou 0001	Capture local information in shape representation.	Multim. Tools Appl.	2007	DBLP DOI BibTeX RDF	Component distance distribution function, Local, Image retrieval, Shape representation
19	Lei Zhang 0004, Sushil Jajodia, Alexander Brodsky 0001	Information disclosure under realistic assumptions: privacy versus optimality.	CCS	2007	DBLP DOI BibTeX RDF	disclosure algorithm, privacy preservation, information disclosure
19	Kee-Young Shin, Kang Yong Lee, Kwangyong Lee, Pyeong Soo Mah, Seungmin Park 0001, Heung-Nam Kim	Enhanced Time-Sync Protocol for Embedded Sensor Networks.	VTC Spring	2006	DBLP DOI BibTeX RDF
19	Volnei A. Pedroni	Phase sampling: a new approach to the design of LF direct digital frequency synthesizers.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Kee-Young Shin, Jin Won Kim, Ilgon Park, Pyeong Soo Mah	Wireless Sensor Networks: A Scalable Time Synchronization.	ICCSA (4)	2006	DBLP DOI BibTeX RDF
19	Takanobu Masubuchi, Mitsuyuki Takatsuka, Ryôichi Sasaki	A Digital Document Flexible Sanitizing Scheme.	IIH-MSP	2006	DBLP DOI BibTeX RDF
19	Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu	Digital signal processing engine design for polar transmitter in wireless communication systems.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
19	Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu	A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
19	J. M. Pierre Langlois, Dhamin Al-Khalili	Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
19	Jiandong Jiang, Edward K. F. Lee	Segmented sine wave digital-to-analog converters for frequency synthesizer.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
19	Amr M. Fahim, Mohamed I. Elmasry	A low-power CMOS frequency synthesizer design methodology for wireless applications.	ISCAS (2)	1999	DBLP DOI BibTeX RDF