Search results for "DPGA"

Found 13 publication records. Showing 13 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
76	Maumita Bhattacharya	Handling uncertainty with a real-coded EA.	GECCO (Companion)	2008	DBLP DOI BibTeX RDF	evolutionary algorithm, uncertainty, premature convergence
76	Taejin Park, Ri Choe, Kwang Ryel Ryu	Dual-population genetic algorithm for nonstationary optimization.	GECCO	2008	DBLP DOI BibTeX RDF	dual-population GA, multi-population GA, nonstationary optimization, genetic algorithm, dynamic optimization
73	A. J. Umbarkar, Madhuri Satish Joshi	Serial DPGA vs. Parallel Multithreaded DPGA: Threading Aspects.	SocProS (1)	2011	DBLP DOI BibTeX RDF
51	Taejin Park, Ri Choe, Kwang Ryel Ryu	Adjusting Population Distance for the Dual-Population Genetic Algorithm.	Australian Conference on Artificial Intelligence	2007	DBLP DOI BibTeX RDF	dual-population genetic algorithm, adjusting population distance, multi-modal function optimization, evolutionary algorithm
36	Zi-Rong Jin, Liang Zhang, Zhilong Zou	3D Trajectory Planning of UAV Based on DPGA.	IEEE Access	2021	DBLP DOI BibTeX RDF
36	A. J. Umbarkar, Madhuri Satish Joshi, P. D. Sheth	Diversity-Based Dual-Population Genetic Algorithm (DPGA): A Review.	SocProS (1)	2014	DBLP DOI BibTeX RDF
36	William Anderson, David Carney	Distributed Project Governance Assessment (DPGA): Contextual, hands-on analysis for project governance across sovereign boundaries.	SDG@ICSE	2009	DBLP DOI BibTeX RDF
36	Maumita Bhattacharya	DPGA: A simple distributed population approach to Taclde uncertainty.	IEEE Congress on Evolutionary Computation	2008	DBLP DOI BibTeX RDF
36	André DeHon	DPGA Utilization and Application.	FPGA	1996	DBLP DOI BibTeX RDF
33	Phan Cong Vinh, Jonathan P. Bowen	Formalization of Data Flow Computing and a Coinductive Approach to Verifying Flowware Synthesis.	Trans. Comput. Sci.	2008	DBLP DOI BibTeX RDF	Dynamically Programmable Field Array (DPGA), Flowware, Configware, Configware engineering, Embedded systems, Formal methods, Reconfigurable computing, Dynamic reconfiguration
33	Douglas Chang, Malgorzata Marek-Sadowska	Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Dynamically reconfigurable FPGAs, time-mulitplexed FPGA, Dharma, DPGA, field programmable gate array, partitioning, reconfigurable computing, sequential circuit, force directed scheduling
25	Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama	Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs.	ISVLSI	2005	DBLP DOI BibTeX RDF
25	Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama	Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory.	IPDPS	2005	DBLP DOI BibTeX RDF