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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 27 occurrences of 20 keywords
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Results
Found 28 publication records. Showing 28 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
73 | A. Neslin Ismailoglu, Murat Askar |
SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 566-571, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
56 | Kees van Berkel 0001, Ferry Huberts, Ad M. G. Peeters |
Stretching quasi delay insensitivity by means of extended isochronic forks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 99-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
extended isochronic forks, isochronic-fork assumption, double-rail data paths, DCC error decoder, logic design, asynchronous circuits, asynchronous circuits, arbiter, delay insensitivity, handshake circuits |
50 | Florent Ouchet, Katell Morin-Allory, Laurent Fesquet |
Delay Insensitivity Does Not Mean Slope Insensitivity! ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 16th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2010, Grenoble, France, 3-6 May 2010, pp. 176-184, 2010, IEEE Computer Society, 978-0-7695-4032-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
45 | Frederic Worm, Patrick Thiran, Paolo Ienne |
A Unified Coding Framework for Delay-Insensitivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 201-211, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Pedro A. Molina, Peter Y. K. Cheung |
A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 126-139, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Tri-state Buffers, Asynchronous, Composability, Bus, Data Path, Delay-Insensitive, Handshake Circuits |
30 | Signe J. Silver, Janusz A. Brzozowski |
True Concurrency in Models of Asynchronous Circuit Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 22(3), pp. 183-203, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multiple-winner, single-winner, semi-modular, asynchronous, circuit, interleaving, true concurrency, delay-insensitive |
29 | Willem C. Mallon |
On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 12-22, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
{Communicating Processes}, {Computer Aided Design}, Meta-stability, Formal Methods, Handshake Protocol, Delay-Insensitivity |
29 | Willem C. Mallon, Jan Tijmen Udding, Tom Verhoeff |
Analysis and Applications of the XDI model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 19-22 April 1999, Barcelona, Spain, pp. 231-242, 1999, IEEE Computer Society, 0-7695-0031-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Verification, Factorization, Derivation, Communicating Processes, Delay Insensitivity |
28 | Moez Yeddes, Hassane Alla, René David |
The Partition Method for the Order - Insensitivity in a Synchronous Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the Fifth IEEE Symposium on Computers and Communications (ISCC 2000), 4-6 July 2000, Antibes, France, pp. 635-640, 2000, IEEE Computer Society, 0-7695-0722-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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28 | Weina Wang 0001, Siva Theja Maguluri, R. Srikant 0001, Lei Ying 0001 |
Heavy-Traffic Delay Insensitivity in Connection-Level Models of Data Transfer with Proportionally Fair Bandwidth Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 45(3), pp. 232-245, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Delong Shang, Fei Xia, Stanislavs Golubcovs, Alexandre Yakovlev |
The Magic Rule of Tiles: Virtual Delay Insensitivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers, pp. 286-296, 2009, Springer, 978-3-642-11801-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Ayse Neslin Ismailoglu, Murat Askar |
Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 1063-1066, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Alex Kondratyev, Oriol Roig, Lawrence Neukom, Karl Fant, Alexander Taubin |
Checking Delay-Insensitivity: 104 Gates and Beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 149-157, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
28 | Serban E. Vlad |
The Delay-Insensitivity, the Hazard-Freedom, the Semi-Modularity and the Technical Condition of Good Running of the Discrete Time Asynchronous Automata ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR cs.LO/0110062, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
28 | Janusz A. Brzozowski, Hao Zhang 0002 |
Delay-Insensitivity and Semi-Modularity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 16(2), pp. 191-218, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Janusz A. Brzozowski |
Delay-insensitivity and ternary simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theor. Comput. Sci. ![In: Theor. Comput. Sci. 245(1), pp. 3-25, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev |
What is the cost of delay insensitivity? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 316-323, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Shuvra S. Bhattacharyya |
Asynchrony and delay-insensitivity in computer engineering education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@HPCA ![In: Proceedings of the 1999 workshop on Computer architecture education, WCAE@HPCA 1999, Orlando, FL, USA, January 1999, pp. 7, 1999, ACM, 978-1-4503-4741-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Jia Di, Dilip P. Vasudevan |
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 149-156, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert Cauwenberghs |
Adaptive delay compensation in multi-dithering adaptive control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2182-2185, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | A. Neslin Ismailoglu, Murat Askar |
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3259-3262, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee |
The Design of Delay Insensitive Asynchronous 16-bit Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 33-36, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya |
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 262-273, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit |
15 | P. Balasubramanian 0001, David A. Edwards |
A New Design Technique for Weakly Indicating Function Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 116-121, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu |
Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 44, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Alexandre Yakovlev, Stephen B. Furber, René Krenz, Alexandre V. Bystrov |
Design and Analysis of a Self-Timed Duplex Communication System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(7), pp. 798-814, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Wei Li 0030, Hang Chen, Qing-An Zeng, Dharma P. Agrawal |
Resource allocation for handoffs in integrated wireless cellular networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISICT ![In: Proceedings of the Intenational Symposium on Information and Communication Technologies, Las Vegas, Nevada, USA, June 16-18, 2004, pp. 238-243, 2004, Trinity College Dublin, 1-59593-170-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
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15 | Alessandro De Gloria, Paolo Palma, Mauro Olivieri |
Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1244-1247, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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