Search results for "Delay-Insensitivity"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
73	A. Neslin Ismailoglu, Murat Askar	SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation.	DSD	2008	DBLP DOI BibTeX RDF
56	Kees van Berkel 0001, Ferry Huberts, Ad M. G. Peeters	Stretching quasi delay insensitivity by means of extended isochronic forks.	ASYNC	1995	DBLP DOI BibTeX RDF	extended isochronic forks, isochronic-fork assumption, double-rail data paths, DCC error decoder, logic design, asynchronous circuits, asynchronous circuits, arbiter, delay insensitivity, handshake circuits
50	Florent Ouchet, Katell Morin-Allory, Laurent Fesquet	Delay Insensitivity Does Not Mean Slope Insensitivity!	ASYNC	2010	DBLP DOI BibTeX RDF
45	Frederic Worm, Patrick Thiran, Paolo Ienne	A Unified Coding Framework for Delay-Insensitivity.	ASYNC	2005	DBLP DOI BibTeX RDF
32	Pedro A. Molina, Peter Y. K. Cheung	A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems.	ASYNC	1997	DBLP DOI BibTeX RDF	Tri-state Buffers, Asynchronous, Composability, Bus, Data Path, Delay-Insensitive, Handshake Circuits
30	Signe J. Silver, Janusz A. Brzozowski	True Concurrency in Models of Asynchronous Circuit Behavior.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	multiple-winner, single-winner, semi-modular, asynchronous, circuit, interleaving, true concurrency, delay-insensitive
29	Willem C. Mallon	On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism.	ASYNC	2000	DBLP DOI BibTeX RDF	{Communicating Processes}, {Computer Aided Design}, Meta-stability, Formal Methods, Handshake Protocol, Delay-Insensitivity
29	Willem C. Mallon, Jan Tijmen Udding, Tom Verhoeff	Analysis and Applications of the XDI model.	ASYNC	1999	DBLP DOI BibTeX RDF	Verification, Factorization, Derivation, Communicating Processes, Delay Insensitivity
28	Moez Yeddes, Hassane Alla, René David	The Partition Method for the Order - Insensitivity in a Synchronous Distributed Systems.	ISCC	2000	DBLP DOI BibTeX RDF
28	Weina Wang 0001, Siva Theja Maguluri, R. Srikant 0001, Lei Ying 0001	Heavy-Traffic Delay Insensitivity in Connection-Level Models of Data Transfer with Proportionally Fair Bandwidth Sharing.	SIGMETRICS Perform. Evaluation Rev.	2017	DBLP DOI BibTeX RDF
28	Delong Shang, Fei Xia, Stanislavs Golubcovs, Alexandre Yakovlev	The Magic Rule of Tiles: Virtual Delay Insensitivity.	PATMOS	2009	DBLP DOI BibTeX RDF
28	Ayse Neslin Ismailoglu, Murat Askar	Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic.	ICECS	2008	DBLP DOI BibTeX RDF
28	Alex Kondratyev, Oriol Roig, Lawrence Neukom, Karl Fant, Alexander Taubin	Checking Delay-Insensitivity: 104 Gates and Beyond.	ASYNC	2002	DBLP BibTeX RDF
28	Serban E. Vlad	The Delay-Insensitivity, the Hazard-Freedom, the Semi-Modularity and the Technical Condition of Good Running of the Discrete Time Asynchronous Automata	CoRR	2001	DBLP BibTeX RDF
28	Janusz A. Brzozowski, Hao Zhang 0002	Delay-Insensitivity and Semi-Modularity.	Formal Methods Syst. Des.	2000	DBLP DOI BibTeX RDF
28	Janusz A. Brzozowski	Delay-insensitivity and ternary simulation.	Theor. Comput. Sci.	2000	DBLP DOI BibTeX RDF
28	Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev	What is the cost of delay insensitivity?	ICCAD	1999	DBLP DOI BibTeX RDF
28	Shuvra S. Bhattacharyya	Asynchrony and delay-insensitivity in computer engineering education.	WCAE@HPCA	1999	DBLP DOI BibTeX RDF
22	Jia Di, Dilip P. Vasudevan	Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays.	DELTA	2006	DBLP DOI BibTeX RDF
20	Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert Cauwenberghs	Adaptive delay compensation in multi-dithering adaptive control.	ISCAS	2008	DBLP DOI BibTeX RDF
20	A. Neslin Ismailoglu, Murat Askar	Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee	The Design of Delay Insensitive Asynchronous 16-bit Microprocessor.	ASP-DAC	1999	DBLP DOI BibTeX RDF
17	Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya	Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic.	ASYNC	1998	DBLP DOI BibTeX RDF	pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit
15	P. Balasubramanian 0001, David A. Edwards	A New Design Technique for Weakly Indicating Function Blocks.	DDECS	2008	DBLP DOI BibTeX RDF
15	Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu	Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme.	ISMVL	2007	DBLP DOI BibTeX RDF
15	Alexandre Yakovlev, Stephen B. Furber, René Krenz, Alexandre V. Bystrov	Design and Analysis of a Self-Timed Duplex Communication System.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
15	Wei Li 0030, Hang Chen, Qing-An Zeng, Dharma P. Agrawal	Resource allocation for handoffs in integrated wireless cellular networks.	ISICT	2004	DBLP BibTeX RDF
15	Alessandro De Gloria, Paolo Palma, Mauro Olivieri	Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications.	EUROMICRO	1999	DBLP DOI BibTeX RDF