Search results for "EDIF"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
110	Mark Roberts	CEDIF: A Data Driven EDIF Reader.	DAC	1989	DBLP DOI BibTeX RDF
110	Moe Shahdad	An Interface between VHDL and EDIF.	DAC	1987	DBLP DOI BibTeX RDF
93	Jeehong Yang, Serap A. Savari, Oskar Mencer	An Approach to Graph and Netlist Compression.	DCC	2008	DBLP DOI BibTeX RDF	Graph Compression, Netlist Compression, EDIF Compression, CEDIF, SUBDUE, GRAPHITOUR
83	M. J. van der Westhuizen, R. G. Harley, D. C. Levy, D. R. Woodward	Using EDIF for software generation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	EDIF, parallel microprocessors, codesign methods, hardware development tools, real-time parallel C code, FPGA, parallel programming, simulated annealing, simulated annealing, software tools, software tool, logic CAD, circuit CAD, C language, scheduling theory, software generation, development systems
70	T. C. O. Young, Hilary J. Kahn	A procedural interface to CAD data based on EDIF.	EURO-DAC	1990	DBLP DOI BibTeX RDF
40	Dilvan de Abreu Moreira, Les T. Walczowski	AGENTS a distributed client-server system for leaf cell generation.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	genetic algorithms, software agents, client/server model
40	John P. Eurich	A tutorial introduction to the electronic design interchange format (tutorial session).	DAC	1986	DBLP DOI BibTeX RDF
30	Raphael Fischer 0001, Andreas Pauly, Rahel Wilking, Anoop Kini, David Graurock	Prioritization of Identified Data Science Use Cases in Industrial Manufacturing via C-EDIF Scoring.	DSAA	2023	DBLP DOI BibTeX RDF
30	Dmitry I. Cheremisinov	Design automation tool to generate EDIF and VHDL descriptions of circuit by extraction of FPGA configuration.	EWDTS	2013	DBLP DOI BibTeX RDF
30	Hilary J. Kahn	EDIF version 350/400 and information modeling.	ASP-DAC	1995	DBLP DOI BibTeX RDF
30	Rachel Y. W. Lau, Hilary J. Kahn	Information Modelling of EDIF.	DAC	1993	DBLP DOI BibTeX RDF
30	Bas Verhelst, Richard Morren, Keith Baker	Using EDIF for Transfer of Test Data: Practical Experience.	ITC	1992	DBLP DOI BibTeX RDF
30	Michael G. Wahl, Carol Pyron	EDIF Test - The Upcoming Standard for Test Data Transfers.	ITC	1992	DBLP DOI BibTeX RDF
30	Hilary J. Kahn, Richard Goldman	The Electronic Design Interchange Format EDIF: Present and Future.	DAC	1992	DBLP BibTeX RDF
30	Shankar R. Mukherjee, Maqsoodul Mannan	Switch and logic-level modeling in EDIF 200: limitations and proposed solutions.	EURO-DAC	1991	DBLP BibTeX RDF
30	Gerhard Schäfer	EDIF zur Strukturbeschreibung und Konfiguration eines Simulatorkopplungsverbundes.	ASIM	1991	DBLP BibTeX RDF
30	Carol Pyron	Representing Boundary Scan Tests with the EDIF Test View.	ITC	1991	DBLP DOI BibTeX RDF
30	Wanhao Li, Hart Switzer	A Unified Data Exchange Environment Based on EDIF.	DAC	1989	DBLP DOI BibTeX RDF
30	John P. Eurich	EDIF: Test Generationand Fault Simulation.	COMPCON	1988	DBLP DOI BibTeX RDF
30	Moe Shahdad	An Interface Between VHDL and EDIF.	COMPCON	1988	DBLP DOI BibTeX RDF
30	D. Glas, Wolfgang Felger	EDIF: Eine Methode zum Transfer von Stromlaufsymbolen.	GI Jahrestagung (2)	1988	DBLP DOI BibTeX RDF
30	M. L. Brei	Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation Mechanisms.	DAC	1987	DBLP DOI BibTeX RDF
30	Esther R. Marx	EDIF: The Standard for Workstation Intercommunication.	IEEE Micro	1985	DBLP DOI BibTeX RDF
30	John D. Crawford	EDIF: A Mechanism for the Exchange of Design Information.	IEEE Des. Test	1985	DBLP DOI BibTeX RDF
20	Manuel Rubio del Solar, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido, Miguel A. Vega-Rodríguez	Placement and routing of Boolean functions in constrained FPGAs using a distributed genetic algorithm and local search.	IPDPS	2006	DBLP DOI BibTeX RDF
20	Khaled Benkrid, Samir Belkacemi, Danny Crookes	A logic based approach to hardware abstraction.	FPGA	2003	DBLP DOI BibTeX RDF
20	Khaled Benkrid, Danny Crookes, Abdsamad Benkrid, Samir Belkacemi	A Prolog-Based Hardware Development Environment.	FPL	2002	DBLP DOI BibTeX RDF
20	Justin L. Tripp, Preston A. Jackson, Brad L. Hutchings	Sea Cucumber: A Synthesizing Compiler for FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
20	Brad L. Hutchings, R. Franklin, D. Carver	Assisting Network Intrusion Detection with Reconfigurable Hardware.	FCCM	2002	DBLP DOI BibTeX RDF
20	Svetlana N. Yanushkevich, Piotr Dziurzanski, Vlad P. Shmerko	The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model.	ISMVL	2002	DBLP DOI BibTeX RDF	multiple-valued logic functions, linear word-level expressions, word-level decision diagrams
20	Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting	A CAD Suite for High-Performance FPGA Design.	FCCM	1999	DBLP DOI BibTeX RDF	adaptive computing systems, high-performance FPGA design, FPGAs, configurable computing
20	Robert H. Klenke, Moshe Meyassed, James H. Aylor, Barry W. Johnson, Ramesh Rao, Anup Ghosh	An Integrated Design Environment for Performance and Dependability Analysis.	DAC	1997	DBLP DOI BibTeX RDF
20	Frank H. Huentemann, Utz G. Baitinger	A gate-matrix oriented partitioning approach for multilevel logical networks.	EURO-DAC	1990	DBLP DOI BibTeX RDF
20	Michael Zimmermann, Manfred Geilert	Generation of embedded RAMs with built-in test using object-oriented programming.	EURO-DAC	1990	DBLP DOI BibTeX RDF
20	Wayne H. Wolf	What Is a Design Automation Framework, Anyway? (panel).	DAC	1988	DBLP BibTeX RDF
20	Kung-Chao Chu, Y. Edmund Lien	Technology tracking for VLSI layout design tools.	DAC	1985	DBLP DOI BibTeX RDF