Search results for "FSMD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
93	Khushwinder Jasrotia, Jianwen Zhu	Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis.	ISQED	2004	DBLP DOI BibTeX RDF
82	Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar 0001, S. R. Pentakota, Chris Reade	A Formal Verification Method of Scheduling in High-level Synthesis.	ISQED	2006	DBLP DOI BibTeX RDF
82	Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede	Extended abstract: a race-free hardware modeling language.	MEMOCODE	2005	DBLP DOI BibTeX RDF
73	Nainesh Agarwal, Nikitas J. Dimopoulos	Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing.	SAMOS	2009	DBLP DOI BibTeX RDF
73	Nainesh Agarwal, Nikitas J. Dimopoulos	FSMD partitioning for low power using simulated annealing.	ISCAS	2008	DBLP DOI BibTeX RDF
61	Chandan Karfa, Dipankar Sarkar 0001, Chitta Mandal, P. Kumar	An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
61	Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar 0001, S. R. Pentakota, Chris Reade	Verification of Scheduling in High-level Synthesis.	ISVLSI	2006	DBLP DOI BibTeX RDF
52	Youngsik Kim, Shekhar Kopuri, Nazanin Mansouri	Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD).	ISQED	2004	DBLP DOI BibTeX RDF
52	Enoch Hwang, Frank Vahid, Yu-Chin Hsu	FSMD Functional Partitioning for Low Power.	DATE	1999	DBLP DOI BibTeX RDF
41	Youngsik Kim, Nazanin Mansouri	Automated formal verification of scheduling with speculative code motions.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	formal verification, high level synthesis, automated theorem-proving, speculation
41	Shuqing Zhao, Daniel Gajski	Modeling a new RTL semantics in C++.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
33	Chandan Karfa, Dipankar Sarkar 0001, Chittaranjan A. Mandal, Chris Reade	Hand-in-hand verification of high-level synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FSMD model, formal verification, high-level synthesis, equivalence checking
33	Thomas Müller-Wipperfürth, Richard Hagelauer	Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base.	DATE	1998	DBLP DOI BibTeX RDF	FSMD, VHDL, Statecharts, Graphical Modelling
32	Valery Salauyou	Embedded Processor Design in FPGA by ASMD-FSMD and FSM-Single Techniques.	CISIM	2022	DBLP DOI BibTeX RDF
32	Valery Salauyou, Adam Klimowicz	Digital Device Design by ASMD-FSMD Technique.	CISIM	2021	DBLP DOI BibTeX RDF
32	Syed Saif Abrar, Maksim Jenihhin, Jaan Raik	FSMD RTL design manipulation for clock interface abstraction.	ICACCI	2015	DBLP DOI BibTeX RDF
32	Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang	Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS.	LATS	2015	DBLP DOI BibTeX RDF
32	Kunal Banerjee 0001, Dipankar Sarkar 0001, Chittaranjan A. Mandal	Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
32	Nikolaos Kavvadias, Kostas Masselos	Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation.	ASAP	2012	DBLP DOI BibTeX RDF
32	Soumyadip Bandyopadhyay, Kunal Banerjee 0001, Dipankar Sarkar 0001, Chittaranjan A. Mandal	Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.	VDAT	2012	DBLP DOI BibTeX RDF
32	Nainesh Agarwal, Nikitas J. Dimopoulos	FSMD Partitioning for Low Power Using ILP.	ISVLSI	2008	DBLP DOI BibTeX RDF
32	Jianwen Zhu, Daniel Gajski	A unified formal model of ISA and FSMD.	CODES	1999	DBLP DOI BibTeX RDF
32	Richard Auletta, Robert B. Reese, Cherrice Traver	A Comparison of Synchronous and Asynchronous FSMD Designs.	ICCD	1993	DBLP DOI BibTeX RDF
20	ChangRyul Yun, DongSoo Kang, YoungHwan Bae, Hanhn Cho, KyoungSon Jhang	Automatic interface synthesis based on the classification of interface protocols of IPs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
20	Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar 0001, Chris Reade	Register Sharing Verification During Data-Path Synthesis.	ICCTA	2007	DBLP DOI BibTeX RDF
20	Monjur Alam, Sonai Ray, Debdeep Mukhopadhyay, Santosh Ghosh, Dipanwita Roy Chowdhury, Indranil Sengupta 0001	An area optimized reconfigurable encryptor for AES-Rijndael.	DATE	2007	DBLP DOI BibTeX RDF
20	Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede	Design with race-free hardware semantics.	DATE	2006	DBLP DOI BibTeX RDF
20	Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto	Design of VHDL-based totally self-checking finite-state machine and data-path descriptions.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
20	Daniel D. Gajski, Loganath Ramachandran	Introduction to High-Level Synthesis.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF