Search results for "Floor-planning"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Gopalakrishnan Vijayan, Ren-Song Tsay	A new method for floor planning using topological constraint reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
62	Chien-Chih Liao, Hsueh-I Lu, Hsu-Chun Yen	Floor-Planning via Orderly Spanning Trees.	GD	2001	DBLP DOI BibTeX RDF
51	Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim	Profile-guided microarchitectural floor planning for deep submicron processor design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
36	Grazia Arato, Giuseppe Bussolino, Anna M. Fiammengo, Roberto Manione	ACCORDO: second generation floor planning.	EURO-DAC	1990	DBLP DOI BibTeX RDF
29	Yi-Hui Cheng, Yao-Wen Chang	Integrating buffer planning with floorplanning for simultaneous multi-objective optimization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
28	Christian Masson, Denis Barbier, Remy Escassut, Daniel Winer, Gregory Chevallier, Pierre François Zeegers	CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP.	EURO-DAC	1990	DBLP DOI BibTeX RDF
28	B. Lokanathan, Edwin Kinnen	Performance optimized floor planning by graph planarization.	DAC	1989	DBLP DOI BibTeX RDF
26	Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin	Automatic bus macro placement for partially reconfigurable FPGA designs.	FPGA	2009	DBLP DOI BibTeX RDF	emips, reconfigurable computing, dynamic partial reconfiguration, floor-planning
26	Husain Parvez, Zied Marrakchi, Habib Mehrez	Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs.	ReConFig	2008	DBLP DOI BibTeX RDF	Coarse-grained FPGA, Exploration environment, Floor-planning
26	Jayaram Bhasker, Sartaj Sahni	A linear algorithm to find a rectangular dual of a planar triangulated graph.	DAC	1986	DBLP DOI BibTeX RDF	planar triagulated graph, rectangular dual, algorithm, complexity, floor planning
22	Alexandra Melike Brintrup, Hideyuki Takagi, Jeremy J. Ramsden	Evaluation of Sequential, Multi-objective, and Parallel Interactive Genetic Algorithms for Multi-objective Floor Plan Optimisation.	EvoWorkshops	2006	DBLP DOI BibTeX RDF
19	Amit K. Gupta II, Appa Iyer Sivakumar, Sumit Sarawgi	Scheduling & control: shop floor scheduling with simulation based proactive decision support.	WSC	2002	DBLP DOI BibTeX RDF
17	Venkateswari Pichaimani, Manjula Ramakrishama Kalava	Linear feature projective geometric damped convolutional deep belief network for indoor floor planning.	J. Intell. Fuzzy Syst.	2023	DBLP DOI BibTeX RDF
17	R. Karthick, A. Senthilselvi, P. Meenalochini	An Optimal Partitioning and Floor Planning for VLSI Circuit Design Based on a Hybrid Bio-Inspired Whale Optimization and Adaptive Bird Swarm Optimization (WO-ABSO) Algorithm.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
17	Pushpalatha Pondreti, Babulu Kaparapu	Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization.	Int. J. Swarm Intell. Res.	2023	DBLP DOI BibTeX RDF
17	S. B. Vinay Kumar, P. V. Rao, Manoj Kumar Singh	Optimal floor planning in VLSI using improved adaptive particle swarm optimization.	Evol. Intell.	2022	DBLP DOI BibTeX RDF
17		Positioning of WiFi devices for indoor floor planning using principal featured Kohonen deep structure.	J. Ambient Intell. Humaniz. Comput.	2021	DBLP DOI BibTeX RDF
17	Sivakumar Pothiraj, Jeya Prakash Kadambarajan, Pandiaraj Kadarkarai	Floor Planning of 3D IC Design Using Hybrid Multi-verse Optimizer.	Wirel. Pers. Commun.	2021	DBLP DOI BibTeX RDF
17	Jonathan Klawitter, Felix Klesen, Alexander Wolff 0001	Algorithms for Floor Planning with Proximity Requirements.	CoRR	2021	DBLP BibTeX RDF
17	Jonathan Klawitter, Felix Klesen, Alexander Wolff 0001	Algorithms for Floor Planning with Proximity Requirements.	CAAD Futures	2021	DBLP DOI BibTeX RDF
17	Hamide Ozlem Dalgic, Erkan Bostanci, Mehmet Serdar Güzel	Genetic Algorithm Based Floor Planning System.	CoRR	2017	DBLP BibTeX RDF
17	Makoto Inoue, Muneyuki Unehara, Koichi Yamada, Megumu Hiramoto, Hideyuki Takagi	Evaluation of hybrid optimization with EMO and IEC for architectural floor planning.	SCIS&ISIS	2014	DBLP DOI BibTeX RDF
17	Paul Horn, Gabor Lippner	Two Layer 3D Floor Planning.	Electron. J. Comb.	2013	DBLP DOI BibTeX RDF
17	Paul Horn, Gabor Lippner	Two Layer 3D Floor Planning	CoRR	2012	DBLP BibTeX RDF
17	Jaren Lamprecht, Brad L. Hutchings	Profiling FPGA floor-planning effects on timing closure.	FPL	2012	DBLP DOI BibTeX RDF
17	Huaming Zhang, Sadish Sadasivam	Improved floor-planning of graphs via adjacency-preserving transformations.	J. Comb. Optim.	2011	DBLP DOI BibTeX RDF
17	Makoto Inoue, Hideyuki Takagi	EMO-based Architectural Room Floor Planning.	SMC	2009	DBLP DOI BibTeX RDF
17	Bikram Garg, Ashish Agrawal, Rajeev Sehgal, Amarpal Singh, Manish Khanna	Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist.	EWDTS	2008	DBLP DOI BibTeX RDF
17	Maciej Kurowski	Simple and efficient floor-planning.	Inf. Process. Lett.	2003	DBLP DOI BibTeX RDF
17	Chien-Chih Liao, Hsueh-I Lu, Hsu-Chun Yen	Compact floor-planning via orderly spanning trees.	J. Algorithms	2003	DBLP DOI BibTeX RDF
17	Samir Roy, Sanghamitra Bandyopadhyay, Ujjwal Maulik	Evolutionary Approach to Solve the Complex-Triangle Elimination (CTE) Problem of VLSI Floor-planning.	IICAI	2003	DBLP BibTeX RDF
17	Chien-Chih Liao, Hsueh-I Lu, Hsu-Chun Yen	Compact Floor-Planning via Orderly Spanning Trees	CoRR	2002	DBLP BibTeX RDF
17	Kok-Hoo Yeap, Majid Sarrafzadeh	Floor-Planning by Graph Dualization: 2-Concave Rectilinear Modules.	SIAM J. Comput.	1993	DBLP DOI BibTeX RDF
17	Christian Masson, Remy Escassut, Denis Barbier, Daniel Winer, Gregory Chevallier	Object Oriented Lisp Implementation of the CHEOPS VLSI Floor Planning and Routing System.	DAC	1991	DBLP DOI BibTeX RDF	LISP
17	Wing K. Luk, Alvar A. Dean, John W. Mathews	Partitioning and floor-planning for data-path chip (microprocessor) layout.	Integr.	1990	DBLP DOI BibTeX RDF
17	Marwan A. Jabri, David J. Skellern	PIAF: efficient IC floor planning.	IEEE Expert	1989	DBLP DOI BibTeX RDF
17	Wing K. Luk, Alvar A. Dean, John W. Mathews	Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout.	ICCAD	1989	DBLP DOI BibTeX RDF
17	Michael C. McFarland	A fast floor planning algorithm for architectural evaluation.	ICCD	1989	DBLP DOI BibTeX RDF
17	Wayne Wei-Ming Dai, Ernest S. Kuh	Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1987	DBLP DOI BibTeX RDF
17	Yu-Chin Hsu	Floor Planning and Global Routing in an Automated Chip Design System		1987	RDF
17	Howard S. Rifkin, William R. Heller, Steve Law, Misha Burich, Alberto L. Sangiovanni-Vincentelli	Floor planning systems (panel session).	DAC	1986	DBLP DOI BibTeX RDF
14	Victor O. Aken'Ova, Resve A. Saleh	A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm.	ISVLSI	2006	DBLP DOI BibTeX RDF
11	Brett Feero, Partha Pratim Pande	Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
11	Shashank Prasad, Anuj Kumar	Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	Yu Cheng 0001, Tao Zhang 0006, Song Chen	VisionSynaptics: a system convert hand-writing and image symbol into computer symbol.	ICIS	2009	DBLP DOI BibTeX RDF	graphics segmenting, human-computer interaction, intelligent system, symbol recognition
11	Akshaya Kumar Mishra, Justin A. Eichel, Paul W. Fieguth, David A. Clausi	VizDraw: A Platform to Convert Online Hand-Drawn Graphics into Computer Graphics.	ICIAR	2009	DBLP DOI BibTeX RDF	Online hand-drawn diagram recognition, hypothesis generation and evaluation, stroke-based recognition
11	Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger	An 8x8 run-time reconfigurable FPGA embedded in a SoC.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, RTR
11	Lijun Gao, Keshab K. Parhi	Models for Architectural Power and Power Grid Noise Analysis on Data Bus.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	augmented DBT model, SCTA model, STCTA model, power consumption, switching activity, power spectrum, transition probability, power grid noise, transition activity
11	Rajarshi Mukhopadhyay, S. W. Yoon, Y. Park, Chang-Ho Lee, S. Nuttinck, Joy Laskar	Investigation of inductors for digital Si-CMOS technologies.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Alexandra Melike Brintrup, Jeremy J. Ramsden, Ashutosh Tiwari	Integrated qualitativeness in design by multi-objective optimization and interactive evolutionary computation.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
11	Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz	The ISPD2005 placement contest and benchmark suite.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI placement, benchmarks, physical design
11	Chi-Sheng Shih 0001, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen	Reconfigurable Platform for Content Science Research.	RTCSA	2005	DBLP DOI BibTeX RDF
11	Yu-Liang Wu, Chi-Kong Chan	On Improved Least Flexibility First Heuristics Superior for Packing and Stock Cutting Problems.	SAGA	2005	DBLP DOI BibTeX RDF
11	Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov	Unification of partitioning, placement and floorplanning.	ICCAD	2004	DBLP DOI BibTeX RDF
11	Erik Larsson	Integrating Core Selection in the SOC Test Solution Design-Flow.	ITC	2004	DBLP DOI BibTeX RDF
11	Ashwin K. Kumaraswamy, Ahmet T. Erdogan, Indrajit Atluri	Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis.	IWSOC	2004	DBLP DOI BibTeX RDF
11	Erik Larsson, Hideo Fujiwara	Test Resource Partitioning and Optimization for SOC Designs.	VTS	2003	DBLP DOI BibTeX RDF
11	Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang	Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.	DATE	2002	DBLP DOI BibTeX RDF
11	Michael Affenzeller, Franz Pichler, Rudolf Mittelmann	On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata.	EUROCAST	2001	DBLP DOI BibTeX RDF
11	Kyumyung Choi, Steven P. Levitan	A flexible datapath allocation method for architectural synthesis.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	allocation and binding, high-level synthesis
11	Christos A. Papachristou, Yusuf Alzazeri	A Method of Distributed Controller Design for RTL Circuits.	DATE	1999	DBLP DOI BibTeX RDF
11	Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky	On wirelength estimations for row-based placement.	ISPD	1998	DBLP DOI BibTeX RDF