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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
270 | Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev |
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 427-432, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Electrostatic discharge (ESD), electrical overstress (EOS), LVTSCR, latch-up, burn-in |
36 | Xiaomei Fan, Zhihua Zhu, Yingtao Zhang, Ruike Chen, Yao Wang, Juin Jei Liou |
An Improved LVTSCR Device with an Embedded BJT for ESD Protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIE ![In: 30th IEEE International Symposium on Industrial Electronics, ISIE 2021, Kyoto, Japan, June 20-23, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9023-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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36 | Songyan Wang, Xiaomei Fan, Zhihua Zhu, Yingtao Zhang, Ruike Chen, Juin Jei Liou |
A LVTSCR-Based Compact Structure for Latch-up Immune. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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36 | Vladislav A. Vashchenko, Ann Concannon, Marcel ter Beek, P. Hopper |
LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 43(1), pp. 61-69, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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36 | A. Guilhaume, Philippe Galy, J. P. Chante, B. Foucher, F. Blanc |
Simulation and experimental comparison of GGNMOS and LVTSCR protection cells under ElectroStatic Discharges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 41(9-10), pp. 1433-1437, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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36 | Ming-Dou Ker |
ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(8), pp. 1293-1296, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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36 | Ming-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Tao Cheng, Tain-Shun Wu |
Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 833-836, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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