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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8 occurrences of 5 keywords
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Results
Found 12 publication records. Showing 12 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
200 | Thomas Popp, Stefan Mangard |
Implementation aspects of the DPA-resistant logic style MDPL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
181 | Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad T. Manzuri Shalmani |
Power Analysis Attacks on MDPL and DRSL Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2007, 10th International Conference, Seoul, Korea, November 29-30, 2007, Proceedings, pp. 259-272, 2007, Springer, 978-3-540-76787-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DRSL, MDPL, Side-Channel Attacks, DPA, flip-flop |
169 | Thomas Popp, Mario Kirschbaum, Stefan Mangard |
Practical Attacks on Masked Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2009, The Cryptographers' Track at the RSA Conference 2009, San Francisco, CA, USA, April 20-24, 2009. Proceedings, pp. 211-225, 2009, Springer, 978-3-642-00861-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
DPA-Resistant Masked Logic Styles, MDPL, Prototype Chip, Hardware AES, PDF-Attack, PRNG |
164 | Daisuke Suzuki, Minoru Saeki |
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 255-269, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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134 | Thomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard |
Evaluation of the Masked Logic Style MDPL on a Prototype Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings, pp. 81-94, 2007, Springer, 978-3-540-74734-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DPA-Resistant Logic Styles, Masked Logic, Dual-Rail Precharge Logic, Early Propagation Effect, Improved MDPL, Prototype Chip |
122 | Benedikt Gierlichs |
DPA-Resistance Without Routing Constraints? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings, pp. 107-120, 2007, Springer, 978-3-540-74734-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Differential Side Channel Analysis, DSCA, Masked Dual-rail Pre-charge Logic, MDPL, Gate-level masking, DRP |
99 | Thomas Popp, Stefan Mangard |
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings, pp. 172-186, 2005, Springer, 3-540-28474-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Hardware Countermeasures, MDPL, Masking Logic, Dual-Rail Pre-Charge Logic, DPA, Side-Channel Analysis |
36 | Zhao Zhang 0001, Yulin Sun, Zheng Zhang 0006, Yang Wang 0023, Lin Wu 0001, Meng Wang 0001 |
MDPL-net: Multi-layer Dictionary Learning Network with Added Skip Dense Connections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDM ![In: 20th IEEE International Conference on Data Mining, ICDM 2020, Sorrento, Italy, November 17-20, 2020, pp. 811-820, 2020, IEEE, 978-1-7281-8316-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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36 | Elke De Mulder, Benedikt Gierlichs, Bart Preneel, Ingrid Verbauwhede |
Practical DPA Attacks on MDPL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2009, pp. 231, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
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36 | Elke De Mulder, Benedikt Gierlichs, Bart Preneel, Ingrid Verbauwhede |
Practical DPA attacks on MDPL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WIFS ![In: First IEEE International Workshop on Information Forensics and Security, WIFS 2009, London, UK, December 6-9, 2009, pp. 191-195, 2009, IEEE, 978-1-4244-5279-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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36 | Amir Moradi 0001, Thomas Eisenbarth 0001, Axel Poschmann, Christof Paar |
Power Analysis of Single-Rail Storage Elements as Used in MDPL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information, Security and Cryptology - ICISC 2009, 12th International Conference, Seoul, Korea, December 2-4, 2009, Revised Selected Papers, pp. 146-160, 2009, Springer, 978-3-642-14422-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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23 | Zhimin Chen, Yujie Zhou |
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 242-254, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA |
Displaying result #1 - #12 of 12 (100 per page; Change: )
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