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Found 46124 publication records. Showing 46122 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
91Soo Ho Chang, Soo Dong Kim Reuse-based Methodology in Developing System-on-Chip (SoC). Search on Bibsonomy SERA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
63Bing Guo, Yan Shen, Yue Huang, Zhishu Li A Novel Discrete Hopfield Neural Network Approach for Hardware-Software Partitioning of RTOS in the SoC. Search on Bibsonomy EUC Workshops The full citation details ... 2006 DBLP  DOI  BibTeX  RDF SoC, RTOS, Hopfield neural network, Hardware-software partitioning
63Yves Mathys, André Chátelain Verification strategy for integration 3G baseband SoC. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF 3G baseband, verification, architecture, SoC
62Sudeep Pasricha, Mohamed Ben-Romdhane Using TLM for Exploring Bus-based SoC Communication Architectures. Search on Bibsonomy ASAP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
58Anil Deshpande Verification of IP-Core Based SoC's. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Verification, SoC, Moore's Law
56Yung-Yuan Chen, Chung-Hsien Hsu, Kuen-Long Leu SoC-level risk assessment using FMEA approach in system design with SystemC. Search on Bibsonomy SIES The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
56Du Wan Cheun, Tae Kwon Yu, Soo Ho Chang, Soo Dong Kim A Technical Assessment of SoC Methodologies and Requirements for a Full-Blown Methodology. Search on Bibsonomy ICCSA (2) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Sandeep Kumar Goel, Erik Jan Marinissen SOC test architecture design for efficient utilization of test bandwidth. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF TAM and wrapper design, idle bits, lower bound, test scheduling, SOC test, bandwidth utilization
52Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy On Concurrent Test of Core-Based SOC Design. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF concurrent SOC test, pin mapping, 2-dimensional bin-packing, test scheduling
51Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Chin-Long Wey PrSoC: Programmable System-on-chip (SoC) for silicon prototyping. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
51Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu STEAC: A Platform for Automatic SOC Test Integration. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
50Yen-Kuang Chen, Sun-Yuan Kung Trend and Challenge on System-on-a-Chip Designs. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF SoC design trend, SoC design challenge, VLSI, SoC, system-on-a-chip
47Anuja Sehgal, Krishnendu Chakrabarty Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Full-chip testing, dual-speed TAM, TAM optimization, test scheduling, test access mechanism, SOC testing
47Frédéric Flouvat, Jean-François N'guyen Van Soc, Elise Desmier, Nazha Selmaoui-Folcher Domain-driven co-location mining - Extraction, visualization and integration in a GIS. Search on Bibsonomy GeoInformatica The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
47Martin P. Calasan, Nikola Soc, Vladan Vujicic, Gojko Joksimovic, Chen Hao, Qianglong Wang, Xing Wang Review of marine current speed and power coefficient - Mathematical models. Search on Bibsonomy MECO The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
46Vincenzo Rana, David Atienza, Marco D. Santambrogio, Donatella Sciuto, Giovanni De Micheli A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
46Wolfgang Mueller, Yves Vanderperren UML and model-driven development for SoC design. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF simulation, UML, SoC, tools, SystemC, UML profiles, ESL design
46Young-Sin Cho, Eun-Ju Choi, Kyoung-Rok Cho Modeling and analysis of the system bus latency on the SoC platform. Search on Bibsonomy SLIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF multi-layer bus, system bus, SoC, latency, platform
46Nobuyuki Ohba, Kohji Takano An SoC design methodology using FPGAs and embedded microprocessors. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF mixed-level verification, SoC, ASIC, FPGA prototyping
46Wei-Tek Tsai, Yinong Chen, Xin Sun 0003 Designing a Service-Oriented Computing Course for High Schools. Search on Bibsonomy ICEBE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Subir K. Roy Top Level SOC Interconnectivity Verification Using Formal Techniques. Search on Bibsonomy MTV The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Tun Li, Sikun Li, Jinshan Yu, Yang Guo 0003 A Novel Collaborative Verification Environment for SoC Co-Verification. Search on Bibsonomy CSCWD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Qiang Xu 0001, Nicola Nicolici Modular SOC testing with reduced wrapper count. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Jean-Pierre Heliot, Florent Parmentier, Marie-Pierre Baron LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume Reduction. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
45Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi 0001, Michael Torla, Catherine H. Gebotys Special Session: Security on SoC. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF sequence charts, simulation, validation methodology
45Kazutoshi Wakabayashi, Takumi Okamoto C-based SoC design flow and EDA tools: an ASIC and system vendorperspective. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
44Hans-Joachim Stolberg, Mladen Berekovic, Sören Moch, Lars Friebe, Mark Bernd Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multimedia, VLSI, system-on-chip, multi-core, surveillance, MPEG-4
44Pradeep K. Khosla, Herman Schmit, Mary Jane Irwin, Narayanan Vijaykrishnan, Tom Cain, Steven P. Levitan, Dave Landis SoC Design Skills: Collaboration Builds a Stronger SoC Design Team. Search on Bibsonomy MSE The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43C. P. Ravikumar, Jari Nurmi Conference Reports. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Melvin Breuer, SOC 2006, SoC design, ITC
42Chih-Pin Su, Cheng-Wen Wu A Graph-Based Approach to Power-Constrained SOC Test Scheduling. Search on Bibsonomy J. Electron. Test. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF test integration, test scheduling, test access mechanism (TAM), SOC testing, test power, system-on-chip (SOC)
42Je-Hoon Lee, Young-Sin Cho, Seok-Man Kim, Kyoung-Rok Cho On-Chip Bus Modeling for Power and Performance Estimation. Search on Bibsonomy SAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF bus modeling, bus latency, SoC, on-chip bus
41Tim Kogel, Heinrich Meyr Heterogeneous MP-SoC: the solution to energy-efficient signal processing. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF energy efficiency, network-on-chip, signal processing, design space exploration, MP-SoC
40Stefan Thanheiser, Lei Liu 0020, Hartmut Schmeck SimSOA: an approach for agent-based simulation and design-time assessment of SOC-based IT systems. Search on Bibsonomy SAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF service-oriented computing (SOC), service-oriented architectures (SOA), agent-based simulation
40P. Subramanian, Jagonda Patil, Manish Kumar Saxena FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications. Search on Bibsonomy IWCMC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
40Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun A 2.6 µW sub-threshold mixed-signal ECG SoC. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF sub-threshold SoC, sub-threshold operation, system on chip, electrocardiogram
40Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He 0001, Zhixiong Zhou, Ting Lei Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF SoC system testing, genetic and evolutionary algorithm, design verification
40Cheol-Hong Moon, Dong-Young Jang, Jong-Nam Choi An SoC System for Real-Time Moving Object Detection. Search on Bibsonomy ICIC (1) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF SoC IP, Image processing, Real-time, Moving Object Detection
40Tse-Chen Yeh, Tsung-Yu Ho, Hung-Yu Chen, Ing-Jer Huang SystemC-Based Design Space Exploration of a 3D Graphics Acceleration SoC for Consumer Electronics. Search on Bibsonomy EUC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF SystemC modeling, 3D graphics SoC, design space exploration, transaction-level modeling
40Cheol-Hong Moon, Sung-Oh Kim An SoC System for the Image Grabber Capable of 2D Scanning. Search on Bibsonomy ICNC (2) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF IMAGE IP, Perpendicular Coordinate Robot IP, TFT-LCD IP, SoC
40Jia-Ming Chen, Chih-Hao Chang, Shau-Yin Tseng, Jenq Kuen Lee, Wei-Kuan Shih Power Aware H.264/AVC Video Player on PAC Dual-Core SoC Platform. Search on Bibsonomy EUC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Dual-Core SoC, H.264/AVC, Power-aware, DVFS
40Krishna Sekar, Sujit Dey LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF LI-BIST, crosstalk test, BIST, SoC test, low-power test
40Rainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer Adapting an SoC to ATE Concurrent Test Capabilities. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF ATE, SoC Test, Concurrent Test, Test Resource Partitioning
40Mahesh Mehendale Challenges in the Design of Embedded Real-time DSP SoCs. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Ozgur Sinanoglu, Erik Jan Marinissen Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Cheol-Hong Moon, Young-Soo Roo, Hwa-Young Kim An SoC Embedded System Implementation Using an Array Sensor. Search on Bibsonomy FSKD (3) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi A UML Based System Level Failure Rate Assessment Technique for SoC Designs. Search on Bibsonomy VTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Miguel Ángel Cristín Valdez, Jaime Adrián Orozco Valera, María Jojutla Olimpia Pacheco Arteaga Estimating Soc in Lead-Acid Batteries Using Neural Networks in a Microcontroller-Based Charge-Controller. Search on Bibsonomy IJCNN The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Terence Chan RaceCheck: A Race Logic Audit Program For SoC Designs. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
39Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF LNA optimization, low noise amplifier, analog synthesis
39Chih-wen Hsueh, Tien-Fu Chen, Rong-Guey Chang, Shi-Wu Lo Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design. Search on Bibsonomy RTCSA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Tool Chain, Architecture, Compiler, System-on-Chip, Real-Time Operating System
39Mohsen Nahvi, André Ivanov Indirect test architecture for SoC testing. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Jinyu Zhan, Nan Sang, Guangze Xiong Formal Co-verification for SoC Design with Colored Petri Net. Search on Bibsonomy ICESS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Keon-Myung Lee, Bong Ki Sohn, Jong Tae Kim, Seung Wook Lee, Ji Hyong Lee, Jae Wook Jeon, Jundong Cho An SoC-Based Context-Aware System Architecture. Search on Bibsonomy KES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Imed Moussa, Thierry Grellier, Giang Nguyen Exploring SW Performance Using SoC Transaction-Level Modeling. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
39Wei-Chang Tsai, Chun-Ming Huang, Jiann-Jenn Wang, Chen-Yi Lee Infrastructure for Education and Research of SOC/IP in Taiwan. Search on Bibsonomy MSE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
38Steve Leibson, Grant Martin Design and verification of complex SoC with configurable, extensible processors. Search on Bibsonomy SoCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37K. Schultz, Ketan Paranjape SOC Debug Challenges and Tools. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37Sanghun Lee, Chanho Lee A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
37Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP
37Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF BFT, scalability, pipelining, bus, MP-SoC
36Victor Grimblatt, Chip-Hong Chang, Ricardo Reis 0001, Anupam Chattopadhyay, Andrea Calimera (eds.) VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended Selected Papers Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
36Moreno Bragaglio, Samuele Germiniani, Graziano Pravadelli Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker Transformative Hardware Design Following the Model-Driven Architecture Vision. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Ming Ming Wong, Lu Chen, Anh Tuan Do An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Thiago Santos Copetti, Tobias Gemmeke, Letícia Maria Bolzani Pöhls A DfT Strategy for Detecting Emerging Faults in RRAMs. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Sarah Azimi, Corrado De Sio, Andrea Portaluri, Luca Sterpone Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source Embedded Static RAMs. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Julie Roux, Katell Morin-Allory, Vincent Beroulle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier, Régis Leveugle FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar 0001 END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Michel Walder, Jean-Michel Portal A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Parya Zolfaghari, Sébastien Le Beux Design of a Reconfigurable Optical Computing Architecture Using Phase Change Material. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
36Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
36Ricardo Reis 0001, Manfred Glesner VLSI-SoC: An Enduring Tradition. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
36Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sánchez 0001, Federico Venini Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
36Manikandan Pandiyan, Geetha Mani Wearable ECG SoC for Wireless Body Area Networks: Implementation with Fuzzy Decision Making Chip. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
36Weisheng Zhao, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yue Zhang 0010, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert High Performance SoC Design Using Magnetic Logic and Memory. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
36Christian Piguet, Ricardo Reis 0001, Dimitrios Soudris (eds.) VLSI-SoC: Design Methodologies for SoC and SiP - 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
36Laura Frigerio, Kellie Marks, Argy Krikelis Timed Coloured Petri Nets for Performance Evaluation of DSP Applications: The 3GPP LTE Case Study. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Alessandro Cilardo, Nicola Mazzocca Time Efficient Dual-Field Unit for Cryptography-Related Processing. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Ian O'Connor, Ilham Hassoune, David Navarro Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Kostas Siozios, Dimitrios Soudris A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Tilo Meister, Jens Lienig, Gisbert Thomke Universal Methodology to Handle Differential Pairs during Pin Assignment. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Andre Guntoro, Manfred Glesner A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Enrico Dallago, Daniele Miatton, Giuseppe Venchi, Valeria Bottarel, Giovanni Frattini, Giulio Ricotti, Monica Schipani Comparison of Two Autonomous AC-DC Converters for Piezoelectric Energy Scavenging Systems. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Vasilis F. Pavlidis, Eby G. Friedman Physical Design Issues in 3-D Integrated Technologies. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Nikolas Kroupis, Dimitrios Soudris Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Christophe Escriba, Remy Fulcrand, Philippe Artillan, David Jugieu, Aurélien Bancaud, Ali Boukabache, Anne Marie Gué, Jean-Yves Fourniols Trapping Biological Species in a Lab-on-Chip Microsystem: Micro Inductor Optimization Design and SU8 Process. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Vassilios Vonikakis, Chryssanthi Iakovidou, Ioannis Andreadis Real-Time Biologically-Inspired Image Exposure Correction. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos Timing Error Detection and Correction by Time Dilation. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Vasilios Kalenteridis, Konstantinos Papathanasiou, Stylianos Siskos Analysis and Design of Charge Pumps for Telecommunication Applications. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz Optimizing SOC Test Resources Using Dual Sequences. Search on Bibsonomy VLSI-SoC (Selected Papers) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
36Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms. Search on Bibsonomy VLSI-SOC The full citation details ... 2001 DBLP  BibTeX  RDF
36Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski Built-in Test of Analog Non-Linear Circuits in a SOC Environment. Search on Bibsonomy VLSI-SOC The full citation details ... 2001 DBLP  BibTeX  RDF
36Shaojun Wei Key technologies of system on chip design. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF IC vendor software, SoC, hardware/software co-design, energy-aware design
36Limin Liu, Ping Yan A Bumpless Switching Scheme for Dynamic Reconfiguration. Search on Bibsonomy CDVE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF bumpless switching, SoC, dynamic reconfiguration
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