Search results for "Micro-architectures"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
55	Vangalur S. Alagar, Ralf Lämmel	Three-Tiered Specification of Micro-architectures.	ICFEM	2002	DBLP DOI BibTeX RDF	UML, interaction, formal methods, frameworks, design patterns, reuse, evolution, object-oriented design, micro-architectures
34	Pramod Ramarao, Akhilesh Tyagi	An Adiabatic Framework for a Low Energy µ-Architecture & Compiler.	Interaction between Compilers and Computer Architectures	2003	DBLP DOI BibTeX RDF
32	Shai Erez, Guy Even	An improved micro-architecture for function approximation using piecewise quadratic interpolation.	ICCD	2008	DBLP DOI BibTeX RDF
26	Boon Seong Ang, Derek Chiou, Larry Rudolph, Arvind	Micro-Architectures of High Performance, Multi-User System Area Network Interface Cards.	IPDPS	2000	DBLP DOI BibTeX RDF	Message Passing Mechanisms, Network Interface Unit Architecture, One-poll Mechanism
24	Yann-Gaël Guéhéneuc, Houari A. Sahraoui, Farouk Zaidi	Fingerprinting Design Patterns.	WCRE	2004	DBLP DOI BibTeX RDF
21	Matthias Christen, Olaf Schenk, Esra Neufeld, Peter Messmer, Helmar Burkhart	Parallel data-locality aware stencil computations on modern micro-architectures.	IPDPS	2009	DBLP DOI BibTeX RDF
21	Lev Kirischian, Irina Terterian, Pil Woo Chun, Vadim Geurkov	Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture.	PARELEC	2004	DBLP DOI BibTeX RDF
21	Carl J. Mauer, Mark D. Hill, David A. Wood 0001	Full-system timing-first simulation.	SIGMETRICS	2002	DBLP DOI BibTeX RDF
21	Salah Merniz, Mohamed Benmohammed	A Scalable Proof Methodology for RISC Processor Designs: A Functional Approach.	ITNG	2008	DBLP DOI BibTeX RDF	State functions, RISC designs, Formal Verification, Functional programming, Micro-architectures
19	Avi Mendelson	Memory management challenges in the power-aware computing era.	ISMM	2006	DBLP DOI BibTeX RDF
18	Liwen Shih	Microprogramming heritage of RISC design.	MICRO	1990	DBLP BibTeX RDF
16	Jason Mars, Neil Vachharajani, Robert Hundt, Mary Lou Soffa	Contention aware execution: online contention detection and response.	CGO	2010	DBLP DOI BibTeX RDF	cross-core interference, dynamic techniques, execution runtimes, online adaptation, multicore, contention
16	Yann-Gaël Guéhéneuc, Giuliano Antoniol	DeMIMA: A Multilayered Approach for Design Pattern Identification.	IEEE Trans. Software Eng.	2008	DBLP DOI BibTeX RDF
16	Javier Garzás, Mario Piattini	Improving Object-Oriented Micro Architectural Design Through Knowledge Systematization.	ER (Workshops)	2005	DBLP DOI BibTeX RDF
16	Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer	An automated exploration framework for FPGA-based soft multiprocessor systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	IPv4 packet forwarding, soft multiprocessors, FPGA, design space exploration, integer linear programming
16	Ilya Wagner, Valeria Bertacco, Todd M. Austin	StressTest: an automatic approach to test generation via activity monitors.	DAC	2005	DBLP DOI BibTeX RDF	directed-random simulation, architectural simulation, high-performance simulation
13	Nikhilesh Singh, Vinod Ganesan, Chester Rebeiro	A Survey of Security Concerns and Countermeasures in Modern Micro-architectures with Transient Execution.	CoRR	2023	DBLP DOI BibTeX RDF
13	Sara Sadat Hoseininasab, Caroline Collange, Steven Derrien	Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis.	ARC	2023	DBLP DOI BibTeX RDF
13	Georgios Passas	VLSI micro-architectures for high-radix crossbars		2012	RDF
13	Giorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos	VLSI micro-architectures for high-radix crossbar schedulers.	NOCS	2011	DBLP DOI BibTeX RDF
13	Dionysios Diamantopoulos, Kostas Siozios, Sotirios Xydis, Dimitrios Soudris	Thermal optimization for micro-architectures through selective block replication.	ICSAMOS	2011	DBLP DOI BibTeX RDF
13	Karthik Swaminathan, Ravindhiran Mukundrajan, Niranjan Soundararajan, Vijaykrishnan Narayanan	Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM.	ISVLSI	2011	DBLP DOI BibTeX RDF
13	Ahmed Belderrar, Segla Kpodjedo, Yann-Gaël Guéhéneuc, Giuliano Antoniol, Philippe Galinier	Sub-graph Mining: Identifying Micro-architectures in Evolving Object-Oriented Software.	CSMR	2011	DBLP DOI BibTeX RDF
13	Edward K. Walters II, J. Eliot B. Moss, Trek S. Palmer, Timothy Richards, Charles C. Weems	CASL: A rapid-prototyping language for modern micro-architectures.	Comput. Lang. Syst. Struct.	2008	DBLP DOI BibTeX RDF
13	Edward K. Walters II, J. Eliot B. Moss, Trek S. Palmer, Timothy Richards, Charles C. Weems	Modeling Modern Micro-architectures using CASL.	IPDPS	2007	DBLP DOI BibTeX RDF
13	Catherine Dezan, Erwan Fabiani, Christophe Gouyen, Loïc Lagadec, Bernard Pottier, Caaliph Andriamisaina, Alix Poungou	Synthèse portable pour micro-architectures à grain fin. Application aux turbo décodeurs et nanofabriques.	Tech. Sci. Informatiques	2006	DBLP DOI BibTeX RDF
13	Steven Balensiefer, Lucas Kreger-Stickles, Mark Oskin	An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures.	ISCA	2005	DBLP DOI BibTeX RDF
13	Praveen Kalla, Jörg Henkel, Xiaobo Sharon Hu	SEA: fast power estimation for micro-architectures.	ASP-DAC	2003	DBLP DOI BibTeX RDF
13	Vasu S. Alagar, Ralf Lämmel	Three-Tiered Specification of Micro-Architectures	CoRR	2002	DBLP BibTeX RDF
13	Marco Ferretti	Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing?	CAMP	2000	DBLP DOI BibTeX RDF	super-pipelined microarchitectures, general purpose microprocessors, Von-Neumann paradigm, image processing, parallel architectures, associated memory, instruction set architectures, massively parallel processors, multimedia extensions, SIMD processing
13	Daniel Kröning, Wolfgang J. Paul, Silvia M. Müller	Proving the Correctness of Pipelined Micro-Architectures.	MBMV	2000	DBLP BibTeX RDF
13	Subrata Dasgupta	A model of clocked micro-architectures for firmware engineering and design automation applications.	MICRO	1984	DBLP BibTeX RDF
13	Takanobu Baba, Katsuhiro Yamazaki, Nobuyuki Hashimoto, Hiroyuki Kanai, Kenzo Okuda, Kazuhiko Hashimoto	Hierarchical Micro-Architectures of a Two-Level Microprogrammed Multiprocessor Computer.	ICPP	1983	DBLP BibTeX RDF
13	Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin B. Cohen, Jamil A. Wakil	Temperature-limited microprocessors: Measurements and design implications.	VLSI Design	2007	DBLP DOI BibTeX RDF
13	Eric Schnarr, Mark D. Hill, James R. Larus	Facile: A Language and Compiler for High-Performance Processor Simulators.	PLDI	2001	DBLP DOI BibTeX RDF	micro-architecture simulation, out-of-order processor simulation, partial evaluation, memoization
13	Shu-Lin Hwang, Feipei Lai	Two Cache Lines Prediction for a Wide-Issue Micro-architecture.	ACSAC	2001	DBLP DOI BibTeX RDF
11	Shrirang M. Yardi, Michael S. Hsiao	Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads.	ICCD	2008	DBLP DOI BibTeX RDF
11	Christoph Denzler, Dominik Gruntz	Design patterns: between programming and software design.	ICSE	2008	DBLP DOI BibTeX RDF	design patterns, software engineering curriculum
11	Ernie Chan, Field G. Van Zee, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn	Satisfying your dependencies with SuperMatrix.	CLUSTER	2007	DBLP DOI BibTeX RDF
11	Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu	A Study of the Performance Potential for Dynamic Instruction Hints Selection.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
11	Eila Niemelä, Juhani Latvakoski	Survey of requirements and solutions for ubiquitous software.	MUM	2004	DBLP DOI BibTeX RDF	ubiquitous computing, adaptability, software architecture, interoperability, pervasive computing
8	Min Li 0001, David Novo, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor	An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders.	SiPS	2008	DBLP DOI BibTeX RDF
8	Koustav Bhattacharya, Nagarajan Ranganathan	A linear programming formulation for security-aware gate sizing.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	dynamic power variance, linear programming., path balancing, differential power analysis, gate sizing
8	Erdem Motuk, Roger F. Woods, Stefan Bilbao, John McAllister	Design Methodology for Real-Time FPGA-Based Sound Synthesis.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
8	Macneil Shonle	Modular-Like Transformations and Style Checking for Crosscutting Programming Concepts.	ICSE Companion	2007	DBLP DOI BibTeX RDF
8	Nirav Dave, Michael Pellauer, S. Gerding, Arvind	802.11a transmitter: a case study in microarchitectural exploration.	MEMOCODE	2006	DBLP DOI BibTeX RDF
8	Giuseppe Pappalardo, Emiliano Tramontana	Automatically discovering design patterns and assessing concern separations for applications.	SAC	2006	DBLP DOI BibTeX RDF	software engineering, design patterns, evolution, software evolution, separation of concerns, computational reflection
8	Ramkumar Jayaseelan, Tulika Mitra, Xianfeng Li	Estimating the Worst-Case Energy Consumption of Embedded Software.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
8	Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie 0001, Narayanan Vijaykrishnan, Karthik Sarpatwari	FLAW: FPGA lifetime awareness.	DAC	2006	DBLP DOI BibTeX RDF	hot carrier effects, time dependent dielecric breakdown, FPGA, electromigration
8	Douglas Samuel Kirk, Marc Roper, Murray Wood	Identifying and Addressing Problems in Framework Reuse.	IWPC	2005	DBLP DOI BibTeX RDF	software reuse, Object-oriented frameworks, software comprehension, framework documentation
8	Evelyn Duesterwald, Calin Cascaval, Sandhya Dwarkadas	Characterizing and Predicting Program Behavior and its Variability.	IEEE PACT	2003	DBLP DOI BibTeX RDF
8	Silvia E. Gordillo, Javier Bazzocco, Gustavo Rossi, Robert Laurini	Designing Evolvable Location Models for Ubiquitous Applications.	OOIS	2003	DBLP DOI BibTeX RDF
8	Antonio Carlos Schneider Beck, Júlio C. B. de Mattos, Flávio Rech Wagner, Luigi Carro	CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator.	SBCCI	2003	DBLP DOI BibTeX RDF
8	Zsolt Balanyi, Rudolf Ferenc	Mining Design Patterns from C++ Source Code.	ICSM	2003	DBLP DOI BibTeX RDF
8	Hangsheng Wang, Li-Shiuan Peh, Sharad Malik	A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers.	Hot Interconnects	2002	DBLP DOI BibTeX RDF
8	James Coplien, Liping Zhao 0001	Symmetry Breaking in Software Patterns.	GCSE	2000	DBLP DOI BibTeX RDF
8	Giuliano Antoniol, Roberto Fiutem, L. Cristoforetti	Using Metrics to Identify Design Patterns in Object-Oriented Software.	IEEE METRICS	1998	DBLP DOI BibTeX RDF	Design patterns, software metrics, design recovery
8	Erich Gamma, Richard Helm, Ralph E. Johnson, John M. Vlissides	Design Patterns: Abstraction and Reuse of Object-Oriented Design.	ECOOP	1993	DBLP DOI BibTeX RDF