Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
94 | Jiri Kadlec, Roman Bartosinski, Martin Danek |
Accelerating Microblaze Floating Point Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 621-624, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
77 | Roman L. Lysecky, Frank Vahid |
Design and implementation of a MicroBlaze-based warp processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(3), pp. 22:1-22:22, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation |
66 | Nathan Jachimiec, Fernando Martinez-Vallina, Jafar Saniie |
CReconfigurable finite field instruction set architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 216-220, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MicroBlaze, embedded development, fast simplex links, galois fields, instruction set extensions, partial reconfiguration, finite field arithmetic, Xilinx, FSL |
61 | Paul E. Marks, Cameron D. Patterson |
Data streaming and simd support for the microblaze architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 277, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
streaming coprocessors, vector units, reconfigurability |
61 | Alexander Klimm, Oliver Sander, Jürgen Becker 0001 |
A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
60 | Manuel Hernandez Calviño, Sergio Ruben Geninatti, José Ignacio Benavides Benítez |
Developing an MMX Extension for the MicroBlaze Soft Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 91-96, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MicroBlaze, FPGA, MMX, FSL |
44 | Mariano López-García, Enrique F. Cantó-Navarro |
FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-5, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Michael Hübner 0001, Katarina Paulsson, Jürgen Becker 0001 |
Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga, Yoshiki Yamaguchi |
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 373-380, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Tero Rissa, Adam Donlin, Wayne Luk |
Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 253-258, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Prashant S. Titare, D. G. Khairnar |
MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 11(3), pp. 156-168, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
28 | Jingchao Zhang, Haofeng Kuang, Peiwen Gao, Liyan Qiao |
An FPGA-based real-time radar coordinate transformation by jointly exploiting MicroBlaze and Programmable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
I2MTC ![In: IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2022, Ottawa, ON, Canada, May 16-19, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-8360-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
28 | Lei Sun, Enchang Sun, Yaping Yu |
Real Time Controllable Multi Channel HD Digital Video Processing System Based on FPGA and MicroBlaze. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAI ![In: ICCAI '21: 2021 7th International Conference on Computing and Artificial Intelligence, Tianjin China, April 23 - 26, 2021, pp. 183-190, 2021, ACM, 978-1-4503-8950-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Ahmed Bellemou, Nadjia Benblidia, Mohamed Anane, Mohamed Issad |
MicroBlaze-Based Multiprocessor Embedded Cryptosystem on FPGA for Elliptic Curve Scalar Multiplication Over Fp. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(3), pp. 1950037:1-1950037:33, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Irune Yarza, Mikel Azkarate-askasua, Kim Grüttner, Wolfgang Nebel |
Real-Time Capable Retargeting of Xilinx MicroBlaze Binaries using QEMU: A Feasibility Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAPIDO ![In: Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Manchester, UK, January 22-24, 2018., pp. 3:1-3:8, 2018, ACM, 978-1-4503-6417-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
28 | Eric Matthews, Lesley Shannon, Alexandra Fedorova |
Shared Memory Multicore MicroBlaze System with SMP Linux Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 9(4), pp. 26:1-26:22, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
28 | Imène Mhadhbi, Nabil Litayem, Slim Ben Othman, Slim Ben Saoud |
Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Complex System Modelling and Control Through Intelligent Soft Computations ![In: Complex System Modelling and Control Through Intelligent Soft Computations, pp. 711-744, 2015, Springer, 978-3-319-12882-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Sören Schreiner, Kim Grüttner, Sven Rosinger, Wolfgang Nebel |
Ein Verfahren zur Bestimmung eines Powermodells von Xilinx MicroBlaze MPSoCs zur Verwendung in Virtuellen Plattformen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2015, Chemnitz, Germany, March 3-4, 2015., pp. 73-82, 2015, Sächsische Landesbibliothek, 978-3-00-048889-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
28 | Mohammed Bahoura, Hassan Ezzaidi |
Real-time implementation of an adaptive noise canceller based on MicroBlaze soft processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: IEEE 28th Canadian Conference on Electrical and Computer Engineering, CCECE 2015, Halifax, NS, Canada, May 3-6, 2015, pp. 1180-1183, 2015, IEEE, 978-1-4799-5827-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Wajdi Farhat, Hassene Faiedh, Chokri Souani, Kamel Besbes |
Embedded system for road sign detection using MicroBlaze. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSD ![In: 12th IEEE International Multi-Conference on Systems, Signals & Devices, SSD 2015, Mahdia, Tunisia, March 16-19, 2015, pp. 1-5, 2015, IEEE, 978-1-4799-1758-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | El Hassan El Mimouni, Mohammed Karim |
A MicroBlaze-based Multiprocessor System on Chip for real-time cardiac monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMCS ![In: 4th International Conference on Multimedia Computing and Systems, ICMCS 2014, Marrakech, Morocco, April 14-16, 2014, pp. 331-336, 2014, IEEE, 978-1-4799-3824-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
28 | Ruben Lumbiarres-Lopez, Mariano López-García, Enrique F. Cantó-Navarro |
Implementation on MicroBlaze of AES algorithm to reveal fake keys against side-channel attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIE ![In: 23rd IEEE International Symposium on Industrial Electronics, ISIE 2014, Istanbul, Turkey, June 1-4, 2014, pp. 1882-1887, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
28 | José M. Granado Criado, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido |
Dual MicroBlaze rekeying processor for group key management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 651-654, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Eric Matthews, Lesley Shannon, Alexandra Fedorova |
Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 224-230, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Fadi Obeidat, Robert H. Klenke |
Microblaze: an application-independent fpga-based profiler (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, FPGA 2011, Monterey, California, USA, February 27, March 1, 2011, pp. 283, 2011, ACM, 978-1-4503-0554-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Fadi Obeidat, Robert H. Klenke |
Introducing MicroBlaze as an infrastructure for performance modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011, San Diego, CA, USA, June 5-6, 2011, pp. 90-93, 2011, IEEE Computer Society, 978-1-4577-0548-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta |
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACAI ![In: International Conference on Advances in Computing and Artificial Intelligence, ACAI '11, Rajpura/Punjab, India - July 21 - 22, 2011, pp. 82-85, 2011, ACM, 978-1-4503-0635-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Swagata Samanta, Soumi Paik, Shreedeep Gangopadhyay, Amlan Chakrabarti |
Processing of Image Data Using FPGA-Based MicroBlaze Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPAGC ![In: High Performance Architecture and Grid Computing - International Conference, HPAGC 2011, Chandigarh, India, July 19-20, 2011. Proceedings, pp. 241-246, 2011, Springer, 978-3-642-22576-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Tamar Kranenburg, Rene van Leuken 0001 |
MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, pp. 997-1000, 2010, IEEE Computer Society, 978-1-4244-7054-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Juan Carlos Díaz Martín, Carolina Gómes-Tostón Gutierrez, Álvaro Cortés Fácila, Juan A. Rico-Gallego |
Issues on Building an MPI Cluster on Microblaze. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings, pp. 220-225, 2010, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Jing Pang, Manuel Pravin, Robert Tanihaha |
MicroBlaze Soft Core Based FPGA Embedded System Design of Tetris Game. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2010 International Conference on Embedded Systems & Applications, ESA 2010, July 12-15, 2010, Las Vegas Nevada, USA, pp. 79-85, 2010, CSREA Press, 1-60132-141-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
28 | Nupur Lodha, Nivesh Rai, Rahul Dubey, Hrishikesh Venkataraman |
Hardware-Software Co-design of QRD-RLS Algorithm with Microblaze Soft Core Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISTM ![In: Information Systems, Technology and Management - Third International Conference, ICISTM 2009, Ghaziabad, India, March 12-13, 2009. Proceedings, pp. 197-207, 2009, Springer, 978-3-642-00404-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Susan Xu, Hugh Pollitt-Smith |
A Multi-MicroBlaze Based SOC System: From SystemC Modeling to FPGA Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: The 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, Shortening the Path from Specification to Prototype, 2-5 June 2008, Monterey, California, USA, pp. 121-127, 2008, IEEE Computer Society, 978-0-7695-3180-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Zdenek Pohl, Milan Tichý |
RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 774-777, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Robert H. Klenke |
Experiences Using the Xilinx Microblaze Softcore Processor and uCLinux in Computer Engineering Capstone Senior Design Projects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE '07, San Diego, CA, USA, June 3-4, 2007, pp. 123-124, 2007, IEEE Computer Society, 0-7695-2849-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Pengcheng Mu, Mickaël Raulet, Jean-François Nezan, Jean-Gabriel Cousin |
Automatic code generation for multi-microblaze system with syndex. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSIPCO ![In: 15th European Signal Processing Conference, EUSIPCO 2007, Poznan, Poland, September 3-7, 2007, pp. 1644-1648, 2007, IEEE, 978-839-2134-04-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
28 | Julian Viejo, Manuel J. Bellido, Alejandro Millán 0001, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos |
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IES ![In: International Symposium on Industrial Embedded Systems, IES 2006, Antibes Juan-Les-Pins, France, October 18-20, 2006, pp. 1-7, 2006, IEEE, 1-4244-0777-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | János Lazányi |
Instruction Set Extension Using Microblaze Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 729-730, 2005, IEEE, 0-7803-9362-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Claus Traulsen, Reinhard von Hanxleden |
Reactive parallel processing for synchronous dataflow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 483-490, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Scade, reactive processors, synchronous languages, parallel execution, synchronous dataflow, Lustre |
16 | Nikos Anastasiadis, Isidoros Sideris, Kiamal Z. Pekmestzi |
A fast multiplier-less edge detection accelerator for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 510-515, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
FPGA, edge detection, coprocessor, FSL |
16 | Omar A. Al Rayahi, Mohammed A. S. Khalid |
UWindsor Nios II: A soft-core processor for design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 451-457, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | David Sheldon, Frank Vahid |
Making good points: application-specific pareto-point generation for design space exploration using statistical methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 123-132, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments |
16 | Xinyu Li, Omar Hammami |
Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 278, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fpga, multiprocessor, network on chip |
16 | Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto |
HW/SW methodologies for synchronization in FPGA multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 265-268, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fpga, synchronization, multiprocessors |
16 | |
Efficient implementation of QRD-RLS algorithm using hardware-software co-design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-4, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Mahdi Elghazali, Ahmed Elhossini, Shawki Areibi |
HW/SW co-design architecture exploration for VLSI maze routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 1188-1193, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Xinming Huang 0001, Cao Liang, Jing Ma 0006 |
System Architecture and Implementation of MIMO Sphere Decoders on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(2), pp. 188-197, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Junfeng Fan, Lejla Batina, Kazuo Sakiyama, Ingrid Verbauwhede |
FPGA Design for Algebraic Tori-Based Public-Key Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1292-1297, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Sebastien Fontaine, Luc Filion, Guy Bois |
Exploring ISS Abstractions for Embedded Software Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 651-655, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Hongzhi Wang 0003, Pierre Leray, Jacques Palicot |
An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 746-750, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Andreas Ehliar, Per Karlström, Dake Liu |
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 599-602, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Enno Lübbers, Marco Platzner |
A portable abstraction layer for hardware threads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 17-22, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Alessio Montone, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto |
HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Faisal Khan, Lihua Yuan, Chen-Nee Chuah, Soheil Ghiasi |
A programmable architecture for scalable and real-time network traffic measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2008, San Jose, California, USA, November 6-7, 2008, pp. 109-118, 2008, ACM, 978-1-60558-346-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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16 | Iván González 0004, Estanislao Aguayo, Sergio López-Buedo |
Self-Reconfigurable Embedded Systems on Low-Cost FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(4), pp. 49-57, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable hardware, real-time and embedded systems, special-purpose and application-based systems, algorithms implemented in hardware |
16 | Gerald Hempel, Christian Hochberger |
A resource optimized Processor Core for FPGA based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 51-58, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz |
RAMP Blue: A Message-Passing Manycore System in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 54-61, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Christoforos Kachris, Stamatis Vassiliadis |
A reconfigurable platform for multi-service edge routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 165-170, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
edge routers, FPGA, reconfigurable logic |
16 | Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann |
Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007, 23-25 April 2007, Napa, California, USA, pp. 283-284, 2007, IEEE Computer Society, 0-7695-2940-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Philip Garcia, Katherine Compton |
A Reconfigurable Hardware Interface for a Modern Computing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007, 23-25 April 2007, Napa, California, USA, pp. 73-84, 2007, IEEE Computer Society, 0-7695-2940-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir |
Supporting multithreading in configurable soft processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 155-159, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
soft processor cores, multithreading |
16 | Henrique C. Freitas, Dalton M. Colombo, Fernanda Lima Kastensmidt, Philippe Olivier Alexandre Navaux |
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3776-3779, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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16 | Naser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi |
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 329-334, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ODYSSEY, embedded systems, ASIP, JPEG |
16 | Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams 0001 |
Multi Stream Cipher Architecture for Reconfigurable System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | María Brox, Santiago Sánchez-Solano |
Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-2, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski |
Generic netlist representation for system and PE level design exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 282-287, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
GNR, NISC, modeling, synthesis, system design, architecture description language, application-specific processor |
16 | Cao Liang, Jing Ma 0006, Xinming Huang 0001 |
Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 339-340, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | J. Gonzalez-Gomez, Iván González, Francisco J. Gomez-Arribas, Eduardo I. Boemo |
Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 24-29, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | David Sheldon, Rakesh Kumar 0002, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky |
Conjoining soft-core FPGA processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 694-701, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning |
16 | Jack Whitham, Neil C. Audsley |
MCGREP - A Predictable Architecture for Embedded Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), 5-8 December 2006, Rio de Janeiro, Brazil, pp. 13-24, 2006, IEEE Computer Society, 0-7695-2761-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Fan Wu, Siyue Chen, Henry Leung |
Data Hiding for Speech Bandwidth Extension and its Hardware Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, ICME 2006, July 9-12 2006, Toronto, Ontario, Canada, pp. 1277-1280, 2006, IEEE Computer Society, 1-4244-0367-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Christoforos Kachris, Stamatis Vassiliadis |
Performance Evaluation of an Adaptive FPGA for Network Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 14-16 June 2006, Chania, Crete, Greece, pp. 54-62, 2006, IEEE Computer Society, 0-7695-2580-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Junho Cho, Hoseok Chang, Wonyong Sung |
An FPGA based SIMD processor with a vector memory unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi |
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 651-656, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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16 | Roman L. Lysecky, Frank Vahid |
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 18-23, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Matthew Ouellette, Daniel A. Connors |
Analysis of Hardware Acceleration in Reconfigurable Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Mounir Boukadoum, Karima Tabari, Abdelhak Bensaoula, David Starikov, El Mostapha Aboulhamid |
FPGA implementation of a CDMA source coding and modulation subsystem for a multiband fluorometer with pattern recognition capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4767-4770, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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16 | Charlie Ross, A. P. Wim Böhm |
Using FIFOs in Hardware-Software Co-Design for FPGA Based Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 318-319, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|