Search results for "MicroBlaze"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Jiri Kadlec, Roman Bartosinski, Martin Danek	Accelerating Microblaze Floating Point Operations.	FPL	2007	DBLP DOI BibTeX RDF
77	Roman L. Lysecky, Frank Vahid	Design and implementation of a MicroBlaze-based warp processor.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
66	Nathan Jachimiec, Fernando Martinez-Vallina, Jafar Saniie	CReconfigurable finite field instruction set architecture.	FPGA	2007	DBLP DOI BibTeX RDF	MicroBlaze, embedded development, fast simplex links, galois fields, instruction set extensions, partial reconfiguration, finite field arithmetic, Xilinx, FSL
61	Paul E. Marks, Cameron D. Patterson	Data streaming and simd support for the microblaze architecture.	FPGA	2009	DBLP DOI BibTeX RDF	streaming coprocessors, vector units, reconfigurability
61	Alexander Klimm, Oliver Sander, Jürgen Becker 0001	A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs.	IPDPS	2009	DBLP DOI BibTeX RDF
60	Manuel Hernandez Calviño, Sergio Ruben Geninatti, José Ignacio Benavides Benítez	Developing an MMX Extension for the MicroBlaze Soft Processor.	ReConFig	2008	DBLP DOI BibTeX RDF	MicroBlaze, FPGA, MMX, FSL
44	Mariano López-García, Enrique F. Cantó-Navarro	FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor.	FPL	2006	DBLP DOI BibTeX RDF
44	Michael Hübner 0001, Katarina Paulsson, Jürgen Becker 0001	Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.	IPDPS	2005	DBLP DOI BibTeX RDF
33	Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga, Yoshiki Yamaguchi	On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition.	AHS	2006	DBLP DOI BibTeX RDF
33	Tero Rissa, Adam Donlin, Wayne Luk	Evaluation of SystemC Modelling of Reconfigurable Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF
28	Prashant S. Titare, D. G. Khairnar	MPSoC design and implementation using microblaze soft core processor architecture for faster execution of arithmetic application.	Int. J. High Perform. Syst. Archit.	2023	DBLP DOI BibTeX RDF
28	Jingchao Zhang, Haofeng Kuang, Peiwen Gao, Liyan Qiao	An FPGA-based real-time radar coordinate transformation by jointly exploiting MicroBlaze and Programmable Logic.	I2MTC	2022	DBLP DOI BibTeX RDF
28	Lei Sun, Enchang Sun, Yaping Yu	Real Time Controllable Multi Channel HD Digital Video Processing System Based on FPGA and MicroBlaze.	ICCAI	2021	DBLP DOI BibTeX RDF
28	Ahmed Bellemou, Nadjia Benblidia, Mohamed Anane, Mohamed Issad	MicroBlaze-Based Multiprocessor Embedded Cryptosystem on FPGA for Elliptic Curve Scalar Multiplication Over Fp.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
28	Irune Yarza, Mikel Azkarate-askasua, Kim Grüttner, Wolfgang Nebel	Real-Time Capable Retargeting of Xilinx MicroBlaze Binaries using QEMU: A Feasibility Study.	RAPIDO	2018	DBLP DOI BibTeX RDF
28	Eric Matthews, Lesley Shannon, Alexandra Fedorova	Shared Memory Multicore MicroBlaze System with SMP Linux Support.	ACM Trans. Reconfigurable Technol. Syst.	2016	DBLP DOI BibTeX RDF
28	Imène Mhadhbi, Nabil Litayem, Slim Ben Othman, Slim Ben Saoud	Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances.	Complex System Modelling and Control Through Intelligent Soft Computations	2015	DBLP DOI BibTeX RDF
28	Sören Schreiner, Kim Grüttner, Sven Rosinger, Wolfgang Nebel	Ein Verfahren zur Bestimmung eines Powermodells von Xilinx MicroBlaze MPSoCs zur Verwendung in Virtuellen Plattformen.	MBMV	2015	DBLP BibTeX RDF
28	Mohammed Bahoura, Hassan Ezzaidi	Real-time implementation of an adaptive noise canceller based on MicroBlaze soft processor.	CCECE	2015	DBLP DOI BibTeX RDF
28	Wajdi Farhat, Hassene Faiedh, Chokri Souani, Kamel Besbes	Embedded system for road sign detection using MicroBlaze.	SSD	2015	DBLP DOI BibTeX RDF
28	El Hassan El Mimouni, Mohammed Karim	A MicroBlaze-based Multiprocessor System on Chip for real-time cardiac monitoring.	ICMCS	2014	DBLP DOI BibTeX RDF
28	Ruben Lumbiarres-Lopez, Mariano López-García, Enrique F. Cantó-Navarro	Implementation on MicroBlaze of AES algorithm to reveal fake keys against side-channel attacks.	ISIE	2014	DBLP DOI BibTeX RDF
28	José M. Granado Criado, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido	Dual MicroBlaze rekeying processor for group key management.	FPL	2012	DBLP DOI BibTeX RDF
28	Eric Matthews, Lesley Shannon, Alexandra Fedorova	Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support.	FPL	2012	DBLP DOI BibTeX RDF
28	Fadi Obeidat, Robert H. Klenke	Microblaze: an application-independent fpga-based profiler (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
28	Fadi Obeidat, Robert H. Klenke	Introducing MicroBlaze as an infrastructure for performance modeling.	MSE	2011	DBLP DOI BibTeX RDF
28	Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta	Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis.	ACAI	2011	DBLP DOI BibTeX RDF
28	Swagata Samanta, Soumi Paik, Shreedeep Gangopadhyay, Amlan Chakrabarti	Processing of Image Data Using FPGA-Based MicroBlaze Core.	HPAGC	2011	DBLP DOI BibTeX RDF
28	Tamar Kranenburg, Rene van Leuken 0001	MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture.	DATE	2010	DBLP DOI BibTeX RDF
28	Juan Carlos Díaz Martín, Carolina Gómes-Tostón Gutierrez, Álvaro Cortés Fácila, Juan A. Rico-Gallego	Issues on Building an MPI Cluster on Microblaze.	ReConFig	2010	DBLP DOI BibTeX RDF
28	Jing Pang, Manuel Pravin, Robert Tanihaha	MicroBlaze Soft Core Based FPGA Embedded System Design of Tetris Game.	ESA	2010	DBLP BibTeX RDF
28	Nupur Lodha, Nivesh Rai, Rahul Dubey, Hrishikesh Venkataraman	Hardware-Software Co-design of QRD-RLS Algorithm with Microblaze Soft Core Processor.	ICISTM	2009	DBLP DOI BibTeX RDF
28	Susan Xu, Hugh Pollitt-Smith	A Multi-MicroBlaze Based SOC System: From SystemC Modeling to FPGA Prototyping.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
28	Zdenek Pohl, Milan Tichý	RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor.	FPL	2007	DBLP DOI BibTeX RDF
28	Robert H. Klenke	Experiences Using the Xilinx Microblaze Softcore Processor and uCLinux in Computer Engineering Capstone Senior Design Projects.	MSE	2007	DBLP DOI BibTeX RDF
28	Pengcheng Mu, Mickaël Raulet, Jean-François Nezan, Jean-Gabriel Cousin	Automatic code generation for multi-microblaze system with syndex.	EUSIPCO	2007	DBLP BibTeX RDF
28	Julian Viejo, Manuel J. Bellido, Alejandro Millán 0001, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos	Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements.	IES	2006	DBLP DOI BibTeX RDF
28	János Lazányi	Instruction Set Extension Using Microblaze Processor.	FPL	2005	DBLP DOI BibTeX RDF
16	Claus Traulsen, Reinhard von Hanxleden	Reactive parallel processing for synchronous dataflow.	SAC	2010	DBLP DOI BibTeX RDF	Scade, reactive processors, synchronous languages, parallel execution, synchronous dataflow, Lustre
16	Nikos Anastasiadis, Isidoros Sideris, Kiamal Z. Pekmestzi	A fast multiplier-less edge detection accelerator for FPGAs.	SAC	2010	DBLP DOI BibTeX RDF	FPGA, edge detection, coprocessor, FSL
16	Omar A. Al Rayahi, Mohammed A. S. Khalid	UWindsor Nios II: A soft-core processor for design space exploration.	EIT	2009	DBLP DOI BibTeX RDF
16	David Sheldon, Frank Vahid	Making good points: application-specific pareto-point generation for design space exploration using statistical methods.	FPGA	2009	DBLP DOI BibTeX RDF	configurable platform, fpga, low-power, exploration, speedup, pruning, pareto-optimal, design of experiments
16	Xinyu Li, Omar Hammami	Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, multiprocessor, network on chip
16	Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	HW/SW methodologies for synchronization in FPGA multiprocessors.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, synchronization, multiprocessors
16		Efficient implementation of QRD-RLS algorithm using hardware-software co-design.	IPDPS	2009	DBLP DOI BibTeX RDF
16	Mahdi Elghazali, Ahmed Elhossini, Shawki Areibi	HW/SW co-design architecture exploration for VLSI maze routing.	CCECE	2009	DBLP DOI BibTeX RDF
16	Xinming Huang 0001, Cao Liang, Jing Ma 0006	System Architecture and Implementation of MIMO Sphere Decoders on FPGA.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Junfeng Fan, Lejla Batina, Kazuo Sakiyama, Ingrid Verbauwhede	FPGA Design for Algebraic Tori-Based Public-Key Cryptography.	DATE	2008	DBLP DOI BibTeX RDF
16	Sebastien Fontaine, Luc Filion, Guy Bois	Exploring ISS Abstractions for Embedded Software Design.	DSD	2008	DBLP DOI BibTeX RDF
16	Hongzhi Wang 0003, Pierre Leray, Jacques Palicot	An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management.	ICC	2008	DBLP DOI BibTeX RDF
16	Andreas Ehliar, Per Karlström, Dake Liu	A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA.	FPL	2008	DBLP DOI BibTeX RDF
16	Enno Lübbers, Marco Platzner	A portable abstraction layer for hardware threads.	FPL	2008	DBLP DOI BibTeX RDF
16	Alessio Montone, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto	HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
16	Faisal Khan, Lihua Yuan, Chen-Nee Chuah, Soheil Ghiasi	A programmable architecture for scalable and real-time network traffic measurements.	ANCS	2008	DBLP DOI BibTeX RDF
16	Iván González 0004, Estanislao Aguayo, Sergio López-Buedo	Self-Reconfigurable Embedded Systems on Low-Cost FPGAs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	reconfigurable hardware, real-time and embedded systems, special-purpose and application-based systems, algorithms implemented in hardware
16	Gerald Hempel, Christian Hochberger	A resource optimized Processor Core for FPGA based SoCs.	DSD	2007	DBLP DOI BibTeX RDF
16	Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz	RAMP Blue: A Message-Passing Manycore System in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
16	Christoforos Kachris, Stamatis Vassiliadis	A reconfigurable platform for multi-service edge routers.	SBCCI	2007	DBLP DOI BibTeX RDF	edge routers, FPGA, reconfigurable logic
16	Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann	Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-Chip.	FCCM	2007	DBLP DOI BibTeX RDF
16	Philip Garcia, Katherine Compton	A Reconfigurable Hardware Interface for a Modern Computing System.	FCCM	2007	DBLP DOI BibTeX RDF
16	Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir	Supporting multithreading in configurable soft processor cores.	CASES	2007	DBLP DOI BibTeX RDF	soft processor cores, multithreading
16	Henrique C. Freitas, Dalton M. Colombo, Fernanda Lima Kastensmidt, Philippe Olivier Alexandre Navaux	Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Naser MohammadZadeh, Morteza NajafVand, Shaahin Hessabi, Maziar Goudarzi	Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	ODYSSEY, embedded systems, ASIP, JPEG
16	Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams 0001	Multi Stream Cipher Architecture for Reconfigurable System-on-Chip.	FPL	2006	DBLP DOI BibTeX RDF
16	María Brox, Santiago Sánchez-Solano	Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
16	Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski	Generic netlist representation for system and PE level design exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	GNR, NISC, modeling, synthesis, system design, architecture description language, application-specific processor
16	Cao Liang, Jing Ma 0006, Xinming Huang 0001	Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms.	FCCM	2006	DBLP DOI BibTeX RDF
16	J. Gonzalez-Gomez, Iván González, Francisco J. Gomez-Arribas, Eduardo I. Boemo	Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors.	ARC	2006	DBLP DOI BibTeX RDF
16	David Sheldon, Rakesh Kumar 0002, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky	Conjoining soft-core FPGA processors.	ICCAD	2006	DBLP DOI BibTeX RDF	conjoined processors, parameterized platforms, soft-core processors, FPGAs, customization, tuning
16	Jack Whitham, Neil C. Audsley	MCGREP - A Predictable Architecture for Embedded Real-Time Systems.	RTSS	2006	DBLP DOI BibTeX RDF
16	Fan Wu, Siyue Chen, Henry Leung	Data Hiding for Speech Bandwidth Extension and its Hardware Implementation.	ICME	2006	DBLP DOI BibTeX RDF
16	Christoforos Kachris, Stamatis Vassiliadis	Performance Evaluation of an Adaptive FPGA for Network Applications.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
16	Junho Cho, Hoseok Chang, Wonyong Sung	An FPGA based SIMD processor with a vector memory unit.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi	Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.	VLSI Design	2006	DBLP DOI BibTeX RDF
16	Roman L. Lysecky, Frank Vahid	A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning.	DATE	2005	DBLP DOI BibTeX RDF
16	Matthew Ouellette, Daniel A. Connors	Analysis of Hardware Acceleration in Reconfigurable Embedded Systems.	IPDPS	2005	DBLP DOI BibTeX RDF
16	Mounir Boukadoum, Karima Tabari, Abdelhak Bensaoula, David Starikov, El Mostapha Aboulhamid	FPGA implementation of a CDMA source coding and modulation subsystem for a multiband fluorometer with pattern recognition capabilities.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
16	Charlie Ross, A. P. Wim Böhm	Using FIFOs in Hardware-Software Co-Design for FPGA Based Embedded Systems.	FCCM	2004	DBLP DOI BibTeX RDF