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Found 23 publication records. Showing 23 according to the selection in the facets
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Authors |
Title |
Venue |
Year |
Link |
Author keywords |
37 | Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu |
A Built-In Self-Repair Scheme for NOR-Type Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 114-119, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Po-Tsang Huang, Wei-Keng Chang, Wei Hwang |
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1301-1304, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Jung-Hoon Lee |
Next High Performance and Low Power Flash Memory Package Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 22(4), pp. 515-520, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
NAND-type, NOR-type, memory localities, buffer or cache memory, flash memory |
29 | Yen-Jen Chang, Yuan-Hong Liao |
Hybrid-Type CAM Design for Both Power and Performance Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(8), pp. 965-974, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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23 | Yue Xu, Yang Huang |
Influence of ISSG tunnel oxide with decoupled plasma nitridation on erase characteristic of NOR-type floating-gate flash memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(7), pp. 1126-1129, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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23 | Rohan Sinha, Bhawana Singh Nirwan, Mohammad S. Hashmi |
A new row decoding architecture for fast wordline charging in NOR type Flash memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015, pp. 1-5, 2015, IEEE Computer Society, 978-1-4799-1743-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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23 | Yue Xu, Chun-bo Wu, Xiaoli Ji, Feng Yan 0002 |
An 8-level 3-bit cell programming technique in NOR-type nano-scaled SONOS memory devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(1), pp. 331-334, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Changmin Jung, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong |
Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011, pp. 390-397, 2011, IEEE, 978-1-61284-914-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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23 | Afaq Ahmad 0001, Ahmed Al-Maashri |
Investigating some special sequence lengths generated in an external exclusive-NOR type LFSR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 34(4), pp. 270-280, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Mohammad Gh. Mohammad, Jalal Fahmi, Omar Al-Terkawi |
Switched Polarity Charge Pump for NOR-type Flash Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 1200-1203, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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23 | Star Sung, Thomas Chang, Juei Lung Chen |
A nor-type MLC ROM with novel sensing scheme for embedded applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 22-25, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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23 | Ilaria Motta, Giancarlo Ragone, Osama Khouri, Guido Torelli, Rino Micheloni |
High-voltage management in single-supply CHE NOR-type flash memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 91(4), pp. 554-568, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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23 | Masayoshi Ohkawa, Hiroshi Sugawara, Naoaki Sudo, Masaru Tsukiji, Ken-ichiro Nakagawa, Masato Kawata, Ken-ichi Oyama, Toshio Takeshima, Shuichi Ohya |
A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(11), pp. 1584-1589, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan |
Improve CAM power efficiency using decoupled match line scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 165-170, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Amitava Majumdar 0001, Sarma B. K. Vrudhula |
Analysis of signal probability in logic circuits using stochastic models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(3), pp. 365-379, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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13 | Kun-Jin Lin, Cheng-Wen Wu |
A Low-Power CAM Design for LZ Data Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(10), pp. 1139-1145, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
LZ77 algorithm, data compression, low power design, Associative memory, content addressable memory, semiconductor memory |
12 | Yongsoo Joo, Yongseok Choi, Jaehyun Park 0005, Chanik Park, Sung Woo Chung, Eui-Young Chung, Naehyuck Chang |
Energy and Performance Optimization of Demand Paging With OneNAND Flash. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 1969-1982, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin |
Variation Analysis of CAM Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 333-338, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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9 | Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu |
Fault-Pattern Oriented Defect Diagnosis for Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 3-8, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Johannes Grad, James E. Stine |
New algorithms for carry propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 396-399, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
carry propagate addition, conditional sum adder, hybrid adder, ling adder, pseudo-complements, reed adder, domino logic, carry-skip adder |
9 | Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu |
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 281-288, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Masaaki Fukuhara, Masahiro Yoshida |
Power consumption of a Hamming distance search CAM using neuron MOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Rino Micheloni, Matteo Zammattio, Giovanni Campardo, Osama Khouri, Guido Torelli |
Hierarchical Sector Biasing Organization for Flash Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA, pp. 29-33, 2000, IEEE Computer Society, 0-7695-0689-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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