Search results for "RC1000"

Found 20 publication records. Showing 20 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
56	Shrutisagar Chandrasekaran, Abbes Amira	High Performance FPGA Implementation of the Mersenne Twister.	DELTA	2008	DBLP DOI BibTeX RDF	RC1000, FPGA, Mersenne Twister, Handel C
20	Silvia Franchini, Antonio Gentile, M. Grimaudo, C. A. Hung, Sandro Impastato, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile	A Sliced Coprocessor for Native Clifford Algebra Operations.	DSD	2007	DBLP DOI BibTeX RDF
20	Jin Wang, Chong Ho Lee	Complete FPGA Implemented Evolvable Image Filters.	MICAI	2006	DBLP DOI BibTeX RDF
20	David Rodríguez 0001, Juan M. Sánchez, Arturo Duran	Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider.	ARC	2006	DBLP DOI BibTeX RDF
20	Salvatore Vitabile, Vincenzo Conti, Giuseppe Lentini, Filippo Sorbello	An Intelligent Sensor for Fingerprint Recognition.	EUC	2005	DBLP DOI BibTeX RDF
20	Alessandro Cilardo, Antonino Mazzeo, Luigi Romano	An FPGA-based Key-Store for Improving the Dependability of Security Services.	WORDS	2005	DBLP DOI BibTeX RDF
20	Jin Wang, Je Kyo Jung, Yong-Min Lee, Chong Ho Lee	Using Reconfigurable Architecture-Based Intrinsic Incremental Evolution to Evolve a Character Classification System.	CIS (1)	2005	DBLP DOI BibTeX RDF
20	Aziz Ahmedsaid, Abbes Amira	Accelerating svd on reconficurable hardware for image denoising.	ICIP	2004	DBLP DOI BibTeX RDF
20	S. Sukhsawas, Khaled Benkrid	A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs.	ISVLSI	2004	DBLP DOI BibTeX RDF
20	Muthukumar Venkatesan, Daggu Venkateshwar Rao	Image Processing Algorithms on Reconfigurable Architecture using HandelC.	DSD	2004	DBLP DOI BibTeX RDF
20	Faycal Bensaali, Abbes Amira	Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic.	FPL	2004	DBLP DOI BibTeX RDF
20	Daggu Venkateshwar Rao, Muthukumar Venkatesan	An Efficient Reconfigurable Architecture and Implementation of Edge Detection Algorithm using Handle-C.	ITCC (2)	2004	DBLP DOI BibTeX RDF
20	Khaled Benkrid, S. Sukhsawas, Danny Crookes, Samir Belkacemi	A single-FPGA implementation of image connected component labelling.	FPGA	2003	DBLP DOI BibTeX RDF
20	Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid	An FPGA-Based Image Connected Component Labeller.	FPL	2003	DBLP DOI BibTeX RDF
20	David Rodríguez Lozano, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido	Reconfigurable Hybrid Architecture for Web Applications.	FPL	2003	DBLP DOI BibTeX RDF
20	Stephanie McBader, Peter Lee 0002	An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems.	IPDPS	2003	DBLP DOI BibTeX RDF
20	Tomoyoshi Kobori, Tsutomu Maruyama	High Speed Computation of Three Dimensional Cellular Automata with FPGA.	FPL	2002	DBLP DOI BibTeX RDF
20	Peter McCurry, Fearghal Morgan, Liam Kilmartin	Xilinx FPGA implementation of an image classifier for object detection applications.	ICIP (3)	2001	DBLP DOI BibTeX RDF
20	Markus Weinhardt, Wayne Luk	Task-Parallel Programming of Reconfigurable Systems.	FPL	2001	DBLP DOI BibTeX RDF
20	Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino	High Speed Computation of Lattice gas Automata with FPFA.	FPL	2000	DBLP DOI BibTeX RDF