Search results for "RTPG"

Found 9 publication records. Showing 9 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Baris Aktemur, Joel Jones, Samuel N. Kamin, Lars Clausen	Optimizing Marshalling by Run-Time Program Generation.	GPCE	2005	DBLP DOI BibTeX RDF
89	Seongmoon Wang, Sandeep K. Gupta 0001	LT-RTPG: a new test-per-scan BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
70	Seongmoon Wang	A BIST TPG for Low Power Dissipation and High Fault Coverage.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
70	Seongmoon Wang	Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.	ITC	2002	DBLP DOI BibTeX RDF
60	Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos	Hybrid-SBST Methodology for Efficient Testing of Processor Cores.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	H-SBST, RTPG, computer architecture, ATPG, functional testing, microprocessor testing, software-based self-test
47	Hao Xu 0010, Wen-Ben Jone, Ranga Vemuri	Accurate energy breakeven time estimation for run-time power gating.	ICCAD	2008	DBLP DOI BibTeX RDF
47	Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng	Pseudo-Functional Scan-based BIST for Delay Fault.	VTS	2005	DBLP DOI BibTeX RDF
42	Seongmoon Wang, Sandeep K. Gupta 0001	LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation.	ITC	1999	DBLP DOI BibTeX RDF
23	Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv	Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF

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