Search results for "STGs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
107	Javier Esparza, Petr Jancar, Alexander Miller	On the Complexity of Consistency and Complete State Coding for Signal Transition Graphs.	ACSD	2006	DBLP DOI BibTeX RDF
88	Tomohiro Yoneda, Chris J. Myers	Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis.	ATVA	2006	DBLP DOI BibTeX RDF
72	Javier Esparza	A Polynomial-Time Algorithm for Checking Consistency of Free-Choice Signal Transition Graphs.	ACSD	2003	DBLP DOI BibTeX RDF
70	Victor Khomenko, Maciej Koutny, Alexandre Yakovlev	Detecting State Coding Conflicts in STGs Using Integer Programming.	DATE	2002	DBLP DOI BibTeX RDF
54	Qingwei Wu, Michael S. Hsiao	State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
54	Qingwei Wu, Michael S. Hsiao	Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal.	ITC	2003	DBLP DOI BibTeX RDF
54	Enric Pastor, Jordi Cortadella, Alex Kondratyev, Oriol Roig	Structural methods for the synthesis of speed-independent circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
52	Walter Vogler, Ben Kangsah	Improved Decomposition of STGs.	ACSD	2005	DBLP DOI BibTeX RDF
49	Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian	Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	isochronic forks, speed independent circuits (SICs), Asynchronous circuits, signal transition graphs (STGs), hazards
36	Susan Elliott Sim, Sukanya Ratanotayanon, Leyna Cotran	Structure transition graphs: An ECG for program comprehension?	ICPC	2009	DBLP DOI BibTeX RDF
36	Mark Schäfer, Walter Vogler, Petr Jancar	Determinate STG Decomposition of Marked Graphs.	ICATPN	2005	DBLP DOI BibTeX RDF
36	Mark Schäfer, Walter Vogler	Component Refinement and CSC Solving for STG Decomposition.	FoSSaCS	2005	DBLP DOI BibTeX RDF
36	Qingwei Wu, Michael S. Hsiao	State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation.	ITC	2004	DBLP DOI BibTeX RDF
36	Kao-Shing Hwang, Ming-Yi Ju	Speed Planning for a Maneuvering Motion.	J. Intell. Robotic Syst.	2002	DBLP DOI BibTeX RDF	speed alteration, space/time graph, maneuvering motion, interface propagation method, trajectory planning
36	Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev	Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings.	ACSD	1998	DBLP DOI BibTeX RDF	CSC conflicts, Petri Nets, unfoldings, asynchronous design
36	Tam-Anh Chu	Synthesis of hazard-free control circuits from asynchronous finite state machines specifications.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
36	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential test generation and synthesis for testability at the register-transfer and logic levels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
34	Jintao Xing, Xiangyuan Kong, Weiwei Xing, Xiang Wei 0007, Jian Zhang, Wei Lu 0010	STGs: construct spatial and temporal graphs for citywide crowd flow prediction.	Appl. Intell.	2022	DBLP DOI BibTeX RDF
34	Ben Kangsah	Structural Decomposition of STGs (PDF / PS)		2015	RDF
34	Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev	Direct Mapping of Low-Latency Asynchronous Controllers From STGs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
34	Sung Tae Jung, Chris J. Myers	Direct synthesis of timed circuits from free-choice STGs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
34	Kuan-Jen Lin, Jih-Wen Kuo, Chen-Shang Lin	Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
34	Kuan-Jen Lin, Chen-Shang Lin	On the verification of state-coding in STGs.	ICCAD	1992	DBLP DOI BibTeX RDF
31	Victor Khomenko	Behaviour-Preserving Transition Insertions in Unfolding Prefixes.	ICATPN	2007	DBLP DOI BibTeX RDF	Petri net unfoldings, transition insertions, encoding conflicts, Petri nets, transformations, asynchronous circuits, STGs
31	Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers	Synthesis of Speed Independent Circuits Based on Decomposition.	ASYNC	2004	DBLP DOI BibTeX RDF	abstraction, synthesis, Decomposition, STGs, speed-independent circuits
18	Panagiotis Sidiropoulos, Vasileios Mezaris, Ioannis Kompatsiaris, Hugo Meinedo, Isabel Trancoso	Multi-modal scene segmentation using scene transition graphs.	ACM Multimedia	2009	DBLP DOI BibTeX RDF	scene segmentation
18	Peter J. Radcliffe, Xinghuo Yu 0001	A New Time Independent Asynchronous Protocol and Its Applications.	IEEE Trans. Ind. Informatics	2007	DBLP DOI BibTeX RDF
18	Victor Khomenko	Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings.	ACSD	2007	DBLP DOI BibTeX RDF
18	Victor Khomenko, Mark Schäfer, Walter Vogler	Output-Determinacy and Asynchronous Circuit Synthesis.	ACSD	2007	DBLP DOI BibTeX RDF	output-determinacy, OR-causality, decomposition, asynchronous circuits, STG
18	Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers	High Level Synthesis of Timed Asynchronous Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
18	Victor Khomenko, Maciej Koutny, Alexandre Yakovlev	Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT.	ACSD	2004	DBLP DOI BibTeX RDF	net unfoldings, partial order techniques, Petri nets, logic synthesis, asynchronous circuits, SAT, signal transition graphs, STG, self-timed circuits
18	Qingwei Wu, Michael S. Hsiao	Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories.	VTS	2004	DBLP DOI BibTeX RDF
18	Agnes Madalinski, Alexandre V. Bystrov, Victor Khomenko, Alexandre Yakovlev	Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design.	DATE	2003	DBLP DOI BibTeX RDF
18	Victor Khomenko, Maciej Koutny, Alexandre Yakovlev	Detecting State Coding Conflicts in STG Unfoldings Using SAT.	ACSD	2003	DBLP DOI BibTeX RDF	complete state coding, CSC, net unfoldings, Petri nets, asynchronous circuits, SAT, signal transition graphs, STG, automated synthesis
18	Agnes Madalinski	CONFRES: Interactive Coding Conflict Resolver Based on Core Visualisation.	ACSD	2003	DBLP DOI BibTeX RDF
18	Walter Vogler, Ralf Wollowski	Decomposition in Asynchronous Circuit Design.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
18	Walter Vogler, Ralf Wollowski	Decomposition in Asynchronous Circuit Design.	FSTTCS	2002	DBLP DOI BibTeX RDF
18	Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto	Symbolic optimization of interacting controllers based onredundancy identification and removal.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
18	Chien-Nan Jimmy Liu, Jing-Yang Jou	An Efficient Functional Coverage Test for HDL Descriptions at RTL.	ICCD	1999	DBLP DOI BibTeX RDF	verification, coverage, FSM, HDL
18	Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten	A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings.	Application and Theory of Petri Nets	1996	DBLP DOI BibTeX RDF
18	Cho W. Moon, Paul R. Stephan, Robert K. Brayton	Specification, synthesis, and verification of hazard-free asynchronous circuits.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF