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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 35 occurrences of 21 keywords
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Results
Found 41 publication records. Showing 41 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
107 | Javier Esparza, Petr Jancar, Alexander Miller |
On the Complexity of Consistency and Complete State Coding for Signal Transition Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 28-30 June 2006, Turku, Finland, pp. 47-56, 2006, IEEE Computer Society, 0-7695-2556-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
88 | Tomohiro Yoneda, Chris J. Myers |
Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis, 4th International Symposium, ATVA 2006, Beijing, China, October 23-26, 2006., pp. 229-244, 2006, Springer, 3-540-47237-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
72 | Javier Esparza |
A Polynomial-Time Algorithm for Checking Consistency of Free-Choice Signal Transition Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 18-20 June 2003, Guimaraes, Portugal, pp. 61-70, 2003, IEEE Computer Society, 0-7695-1887-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
70 | Victor Khomenko, Maciej Koutny, Alexandre Yakovlev |
Detecting State Coding Conflicts in STGs Using Integer Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 338-345, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
54 | Qingwei Wu, Michael S. Hsiao |
State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2275-2282, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Qingwei Wu, Michael S. Hsiao |
Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 281-289, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
54 | Enric Pastor, Jordi Cortadella, Alex Kondratyev, Oriol Roig |
Structural methods for the synthesis of speed-independent circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11), pp. 1108-1129, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
52 | Walter Vogler, Ben Kangsah |
Improved Decomposition of STGs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 6-9 June 2005, St. Malo, France, pp. 244-253, 2005, IEEE Computer Society, 0-7695-2363-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghian |
Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 266-271, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
isochronic forks, speed independent circuits (SICs), Asynchronous circuits, signal transition graphs (STGs), hazards |
36 | Susan Elliott Sim, Sukanya Ratanotayanon, Leyna Cotran |
Structure transition graphs: An ECG for program comprehension? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPC ![In: The 17th IEEE International Conference on Program Comprehension, ICPC 2009, Vancouver, British Columbia, Canada, May 17-19, 2009, pp. 303-304, 2009, IEEE Computer Society, 978-1-4244-3998-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Mark Schäfer, Walter Vogler, Petr Jancar |
Determinate STG Decomposition of Marked Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICATPN ![In: Applications and Theory of Petri Nets 2005, 26th International Conference, ICATPN 2005, Miami, USA, June 20-25, 2005, Proceedings, pp. 365-384, 2005, Springer, 3-540-26301-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Mark Schäfer, Walter Vogler |
Component Refinement and CSC Solving for STG Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FoSSaCS ![In: Foundations of Software Science and Computational Structures, 8th International Conference, FOSSACS 2005, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005, Edinburgh, UK, April 4-8, 2005, Proceedings, pp. 348-363, 2005, Springer, 3-540-25388-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
36 | Qingwei Wu, Michael S. Hsiao |
State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 820-829, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Kao-Shing Hwang, Ming-Yi Ju |
Speed Planning for a Maneuvering Motion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 33(1), pp. 25-44, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
speed alteration, space/time graph, maneuvering motion, interface propagation method, trajectory planning |
36 | Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev |
Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 152-163, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
CSC conflicts, Petri Nets, unfoldings, asynchronous design |
36 | Tam-Anh Chu |
Synthesis of hazard-free control circuits from asynchronous finite state machines specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(1-2), pp. 61-84, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
36 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Sequential test generation and synthesis for testability at the register-transfer and logic levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5), pp. 579-598, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Jintao Xing, Xiangyuan Kong, Weiwei Xing, Xiang Wei 0007, Jian Zhang, Wei Lu 0010 |
STGs: construct spatial and temporal graphs for citywide crowd flow prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 52(11), pp. 12272-12281, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
34 | Ben Kangsah |
Structural Decomposition of STGs (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2015 |
RDF |
|
34 | Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev |
Direct Mapping of Low-Latency Asynchronous Controllers From STGs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6), pp. 993-1009, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Sung Tae Jung, Chris J. Myers |
Direct synthesis of timed circuits from free-choice STGs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3), pp. 275-290, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
34 | Kuan-Jen Lin, Jih-Wen Kuo, Chen-Shang Lin |
Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDAC-ETC-EUROASIC ![In: EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France, pp. 178-183, 1994, IEEE Computer Society, 0-8186-5410-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
34 | Kuan-Jen Lin, Chen-Shang Lin |
On the verification of state-coding in STGs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers, pp. 118-122, 1992, IEEE Computer Society / ACM, 0-8186-3010-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
31 | Victor Khomenko |
Behaviour-Preserving Transition Insertions in Unfolding Prefixes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICATPN ![In: Petri Nets and Other Models of Concurrency - ICATPN 2007, 28th International Conference on Applications and Theory of Petri Nets and Other Models of Concurrency, ICATPN 2007, Siedlce, Poland, June 25-29, 2007, Proceedings, pp. 204-222, 2007, Springer, 978-3-540-73093-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Petri net unfoldings, transition insertions, encoding conflicts, Petri nets, transformations, asynchronous circuits, STGs |
31 | Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers |
Synthesis of Speed Independent Circuits Based on Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 135-145, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
abstraction, synthesis, Decomposition, STGs, speed-independent circuits |
18 | Panagiotis Sidiropoulos, Vasileios Mezaris, Ioannis Kompatsiaris, Hugo Meinedo, Isabel Trancoso |
Multi-modal scene segmentation using scene transition graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Multimedia ![In: Proceedings of the 17th International Conference on Multimedia 2009, Vancouver, British Columbia, Canada, October 19-24, 2009, pp. 665-668, 2009, ACM, 978-1-60558-608-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
scene segmentation |
18 | Peter J. Radcliffe, Xinghuo Yu 0001 |
A New Time Independent Asynchronous Protocol and Its Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Informatics ![In: IEEE Trans. Ind. Informatics 3(2), pp. 143-153, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Victor Khomenko |
Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 10-13 July 2007, Bratislava, Slovak Republic, pp. 137-146, 2007, IEEE Computer Society, 978-0-7695-2902-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Victor Khomenko, Mark Schäfer, Walter Vogler |
Output-Determinacy and Asynchronous Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 10-13 July 2007, Bratislava, Slovak Republic, pp. 147-156, 2007, IEEE Computer Society, 978-0-7695-2902-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
output-determinacy, OR-causality, decomposition, asynchronous circuits, STG |
18 | Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers |
High Level Synthesis of Timed Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 178-189, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Victor Khomenko, Maciej Koutny, Alexandre Yakovlev |
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 16-18 June 2004, Hamilton, Canada, pp. 16-25, 2004, IEEE Computer Society, 0-7695-2077-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
net unfoldings, partial order techniques, Petri nets, logic synthesis, asynchronous circuits, SAT, signal transition graphs, STG, self-timed circuits |
18 | Qingwei Wu, Michael S. Hsiao |
Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 389-405, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Agnes Madalinski, Alexandre V. Bystrov, Victor Khomenko, Alexandre Yakovlev |
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10926-10931, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Victor Khomenko, Maciej Koutny, Alexandre Yakovlev |
Detecting State Coding Conflicts in STG Unfoldings Using SAT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 18-20 June 2003, Guimaraes, Portugal, pp. 51-60, 2003, IEEE Computer Society, 0-7695-1887-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
complete state coding, CSC, net unfoldings, Petri nets, asynchronous circuits, SAT, signal transition graphs, STG, automated synthesis |
18 | Agnes Madalinski |
CONFRES: Interactive Coding Conflict Resolver Based on Core Visualisation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 18-20 June 2003, Guimaraes, Portugal, pp. 243-244, 2003, IEEE Computer Society, 0-7695-1887-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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18 | Walter Vogler, Ralf Wollowski |
Decomposition in Asynchronous Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurrency and Hardware Design ![In: Concurrency and Hardware Design, Advances in Petri Nets, pp. 152-190, 2002, Springer, 3-540-00199-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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18 | Walter Vogler, Ralf Wollowski |
Decomposition in Asynchronous Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: FST TCS 2002: Foundations of Software Technology and Theoretical Computer Science, 22nd Conference Kanpur, India, December 12-14, 2002, Proceedings, pp. 336-347, 2002, Springer, 3-540-00225-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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18 | Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto |
Symbolic optimization of interacting controllers based onredundancy identification and removal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7), pp. 760-772, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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18 | Chien-Nan Jimmy Liu, Jing-Yang Jou |
An Efficient Functional Coverage Test for HDL Descriptions at RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 325-327, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
verification, coverage, FSM, HDL |
18 | Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten |
A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Application and Theory of Petri Nets ![In: Application and Theory of Petri Nets 1996, 17th International Conference, Osaka, Japan, June 24-28, 1996, Proceedings, pp. 346-365, 1996, Springer, 3-540-61363-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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18 | Cho W. Moon, Paul R. Stephan, Robert K. Brayton |
Specification, synthesis, and verification of hazard-free asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(1-2), pp. 85-100, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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