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Searching for Scoreboarding with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1993 (1) 1995 (1) 1998 (1) 2003 (2) 2004 (2)
Publication types (Num. hits)
article(1) inproceedings(6)
Venues (Conferences, Journals, ...)
ASYNC(1) FPGA(1) ICCD(1) Inform. Spektrum(1) MEMOCODE(1) MICRO(1) MSE(1)
Authors
James C. Hoe(2) Roland E. Wunderlich(2) B. Ramakrishna Rau(1) Birgit Sirocic(1) D. K. Arvind 0001(1) Matthias Menge(1) Miroslav N. Velev(1) Peter Marwedel(1) Robert D. Mullins(1) Sudarshan K. Srinivasan(1) Vinod E. F. Rebello(1)
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
72Sudarshan K. Srinivasan, Miroslav N. Velev Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions. Search on Bibsonomy MEMOCODE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33Matthias Menge Superskalare Prozessoren. Search on Bibsonomy Inform. Spektrum The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Scoreboarding, Reservierungseinheit, Competion-Unit, Retirement-Unit, History-Buffer, Reorder-Buffer
33B. Ramakrishna Rau Dynamically scheduled VLIW processors. Search on Bibsonomy MICRO The full citation details ... 1993 DBLP  DOI  BibTeX  RDF multiple operation issue, scoreboarding, dynamic scheduling, out-of-order execution, VLIW processors
25Roland E. Wunderlich, James C. Hoe In-system FPGA prototyping of an itanium microarchitecture. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Roland E. Wunderlich, James C. Hoe In-System FPGA Prototyping of an Itanium Microarchitecture. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Peter Marwedel, Birgit Sirocic Overcoming The Limitations of Traditional Media For Teaching Modern Processor Desing. Search on Bibsonomy MSE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
25D. K. Arvind 0001, Robert D. Mullins, Vinod E. F. Rebello Micronets: a model for decentralising control in asynchronous processor architectures. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF decentralising control, asynchronous processor architectures, micronets, communicating resources, four-phase protocol, hazard avoidance mechanisms, SPICE-level simulations, computer architecture, computer architecture, pipeline processing, processor architectures, fine-grain concurrency
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