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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8 occurrences of 8 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
72 | Sudarshan K. Srinivasan, Miroslav N. Velev |
Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 24-26 June 2003, Mont Saint-Michel, France, Proceedings, pp. 65-74, 2003, IEEE Computer Society, 0-7695-1923-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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33 | Matthias Menge |
Superskalare Prozessoren. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inform. Spektrum ![In: Inform. Spektrum 21(3), pp. 121-130, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Scoreboarding, Reservierungseinheit, Competion-Unit, Retirement-Unit, History-Buffer, Reorder-Buffer |
33 | B. Ramakrishna Rau |
Dynamically scheduled VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas, USA, November 1993, pp. 80-92, 1993, ACM / IEEE Computer Society, 0-8186-5280-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
multiple operation issue, scoreboarding, dynamic scheduling, out-of-order execution, VLIW processors |
25 | Roland E. Wunderlich, James C. Hoe |
In-system FPGA prototyping of an itanium microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 255, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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25 | Roland E. Wunderlich, James C. Hoe |
In-System FPGA Prototyping of an Itanium Microarchitecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 288-294, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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25 | Peter Marwedel, Birgit Sirocic |
Overcoming The Limitations of Traditional Media For Teaching Modern Processor Desing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 102-103, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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25 | D. K. Arvind 0001, Robert D. Mullins, Vinod E. F. Rebello |
Micronets: a model for decentralising control in asynchronous processor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 190-199, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
decentralising control, asynchronous processor architectures, micronets, communicating resources, four-phase protocol, hazard avoidance mechanisms, SPICE-level simulations, computer architecture, computer architecture, pipeline processing, processor architectures, fine-grain concurrency |
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