Search results for "Soft-Cores"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
47	Serafín Olcoz, Ana Castellvi, Maria Garcia, Jose Angel Gomez	Static Analysis Tools for Soft-Core Reviews and Audits.	DATE	1998	DBLP DOI BibTeX RDF	Soft-Cores, management, analysis, VHDL
41	David Sheldon, Rakesh Kumar 0002, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen	Application-specific customization of parameterized FPGA soft-core processors.	ICCAD	2006	DBLP DOI BibTeX RDF
37	T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua	Compiler-directed customization of ASIP cores.	CODES	2002	DBLP DOI BibTeX RDF	soft cores, embedded, customization, ASIP
34	Ozgur Sinanoglu, Tsvetomir Petrov	A non-intrusive isolation approach for soft cores.	DATE	2007	DBLP DOI BibTeX RDF
30	Ehsan Ali, Wanchalerm Pora	Modular transformation of embedded systems from firm-cores to soft-cores.	Int. J. Embed. Syst.	2021	DBLP DOI BibTeX RDF
28	Muhammet Erkoc, Arda Yurdakul	Halftoning soft cores for low-cost digital displays.	ISCIS	2009	DBLP DOI BibTeX RDF
28	Ludovic L'Hours	Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications.	ASAP	2005	DBLP DOI BibTeX RDF
19	Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante	Automatic Generation of Validation Stimuli for Application-Specific Processors.	DATE	2004	DBLP DOI BibTeX RDF
18	Jean-Michel Gorius, Simon Rokicki, Steven Derrien	Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis.	FPT	2022	DBLP DOI BibTeX RDF
18	Gilles Audemard, Jean-Marie Lagniez, Marie Miceli, Olivier Roussel	Identifying Soft Cores in Propositional Formulæ.	ICAART (2)	2022	DBLP DOI BibTeX RDF
18	Katie Lim, Jonathan Balkind, David Wentzlaff	JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores.	FPGA	2019	DBLP DOI BibTeX RDF
18	Alex Hirvonen, Kati Tervo, Heikki Kultala, Pekka Jääskeläinen	AEx: Automated Customization of Exposed Datapath Soft-Cores.	DSD	2019	DBLP DOI BibTeX RDF
18	Katie Lim, Jonathan Balkind, David Wentzlaff	JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores.	CoRR	2018	DBLP BibTeX RDF
18	Pekka Jääskeläinen, Aleksi Tervo, Guillermo Payá Vayá, Timo Viitanen, Nicolai Behmann, Jarmo Takala, Holger Blume	Transport-Triggered Soft Cores.	IPDPS Workshops	2018	DBLP DOI BibTeX RDF
18	Farzad Fatollahi-Fard, David Donofrio, John Shalf, John D. Leidel, Xi Wang 0009, Yong Chen 0001	OpenSoC system architect: An open toolkit for building soft-cores on FPGAs.	FPL	2017	DBLP DOI BibTeX RDF
18	Mariem Makni, Mouna Baklouti, Smaïl Niar, Mohamed Wassim Jmal, Mohamed Abid	A comparison and performance evaluation of FPGA soft-cores for embedded multi-core systems.	IDT	2016	DBLP DOI BibTeX RDF
18	Soumya J., Srijan Tiwary, Santanu Chattopadhyay	Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores.	J. Syst. Archit.	2015	DBLP DOI BibTeX RDF
18	David Castells-Rufas, Eduard Fernandez-Alonso, Jordi Carrabina, Jaume Joven	Sharing FPUs in many-soft-cores.	FPT	2011	DBLP DOI BibTeX RDF
18	Ozgur Sinanoglu, Tsvetomir Petrov	Isolation Techniques for Soft Cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
18	Christian Hochberger, Alexander Weiss	A new methodology for debugging and validation of soft cores.	FPL	2008	DBLP DOI BibTeX RDF
18	Michael Hübner 0001, Katarina Paulsson, Jürgen Becker 0001	Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.	IPDPS	2005	DBLP DOI BibTeX RDF
18	Alessandro Fin, Franco Fummi, Giovanni Perbellini	Soft-cores generation by instruction set analysis.	ISSS	2001	DBLP DOI BibTeX RDF
16	Salim Ouadjaout, Dominique Houzet	Easy SoC Design with VCI SystemC Adapters.	DSD	2004	DBLP DOI BibTeX RDF
16	Dimitris Bakalis, Kostas Adaos, George Alexiou, Dimitris Nikolos, D. Lymperopoulos	EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
14	Marcio Buss, Tony Givargis, Nikil D. Dutt	Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores.	RTSS	2003	DBLP DOI BibTeX RDF
10	Vincenzo Rana, Donatella Sciuto	A novel design framework for the design of reconfigurable systems based on NoCs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	network-on-chip, reconfigurable computing, design flow, mapping algorithm
10	Antonino Tumeo, Simone Borgio, Davide Bosisio, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	A multiprocessor self-reconfigurable JPEG2000 encoder.	IPDPS	2009	DBLP DOI BibTeX RDF
10	Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov	Protecting bus-based hardware IP by secret sharing.	DAC	2008	DBLP DOI BibTeX RDF	cryptography, manufacturing, integrated circuits, computer crime
10	Yinhe Han 0001, Xiaowei Li 0001, Shivakumar Swaminathan, Yu Hu 0001, Anshuman Chandra	Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
10	Yanhong Liu, Alexander Maxiaguine, Samarjit Chakraborty, Wei Tsang Ooi	Processor Frequency Selection for SoC Platforms for Multimedia Applications.	RTSS	2004	DBLP DOI BibTeX RDF
10	Martin Simka, Viktor Fischer, Milos Drutarovský	Hardware-Software Codesign in Embedded Asymmetric Cryptographiy Application - A Case Study.	FPL	2003	DBLP DOI BibTeX RDF