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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 20 occurrences of 20 keywords
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Results
Found 6 publication records. Showing 6 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
104 | Hong Hao, Kanti Bhabuthmal |
Clock controller design in SuperSPARC II microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 124-129, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller |
57 | Wesley K. Kaplow, William Maniatty, Boleslaw K. Szymanski |
Impact of memory hierarchy on program partitioning and scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (2) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 93-102, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
parallel program scheduling, nonlinear cache-miss rates, loop nest execution simulation, architecturally parameterized cache simulator, loop range, cache-miss ratio, loop interchange, iteration-space blocking, program runtime estimation, IBM 9076 SP1, SuperSPARC, scheduling, parallel programming, optimisation, memory hierarchy, processor scheduling, software performance evaluation, memory architecture, cache storage, program optimization, cache performance, program control structures, program partitioning, Intel i860 |
49 | Umesh Krishnaswamy, Isaac D. Scherson |
Micro-Architecture Evaluation Using Performance Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, Philadelphia, Pennsylvania, USA, May 23-26, 1996, pp. 148-159, 1996, ACM, 0-89791-793-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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25 | Umesh Krishnaswamy, Isaac D. Scherson |
A Framework for Computer Performance Evaluation Using Benchmark Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(12), pp. 1325-1338, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Computer performance evaluation, benchmark sets, performance vectors, performance modeling, superscalar processors, vector computers |
25 | Jörn Schneider, Christian Ferdinand |
Pipeline Behavior Prediction for Superscalar Processors by Abstract Interpretation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Languages, Compilers, and Tools for Embedded Systems ![In: Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES'99), Atlanta, Georgia, USA, May 5, 1999, pp. 35-44, 1999, ACM, 1-58113-136-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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25 | Alvin R. Lebeck, David A. Wood 0001 |
Active Memory: A New Abstraction for Memory-System Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, Ottawa, Canada, May 15-19, 1995, pp. 220-231, 1995, ACM, 0-89791-695-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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