Search results for "TICER"

Found 10 publication records. Showing 10 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
88	Bernard N. Sheehan	TICER: realizable reduction of extracted RC circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
48	Bernard N. Sheehan	Realizable Reduction of RC Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
40	Wenhui Yao, Chunxiong Zheng, Zhenya Zhou	Error Analysis on the TICER Approximation.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
40	Limin Hao, Guoyong Shi	High-Dimensional Extension of the TICER Algorithm.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
36	Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang	Aggressive crunching of extracted RC netlists.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	RC reduction, TICER, crunching, node elimination, resistor shorting, time constants, interconnect modeling, elmore delay
24	Zuochang Ye, Dmitry Vasilyev, Zhenhai Zhu, Joel R. Phillips	Sparse implicit projection (SIP) for reduction of general many-terminal networks.	ICCAD	2008	DBLP DOI BibTeX RDF
24	Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail	Realizable reduction of interconnect circuits including self and mutual inductances.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
24	Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter	Realizable reduction of RLC circuits using node elimination.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
24	Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail	Realizable RLCK circuit crunching.	DAC	2003	DBLP DOI BibTeX RDF	crunching, simulation, interconnect, passive, realizable, model order reduction
24	Zhanhai Qin, Chung-Kuan Cheng	Realizable parasitic reduction using generalized Y-Delta transformation.	DAC	2003	DBLP DOI BibTeX RDF	Y-?, parasitic reduction, transformation, model order reduction

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