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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 11 keywords
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Results
Found 4 publication records. Showing 4 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
33 | Francisco Azevedo |
Maxx: Test Pattern Optimisation with Local Search Over an Extended Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Constraints An Int. J. ![In: Constraints An Int. J. 12(4), pp. 507-538, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
PI, Primary input, TG, Test generation, Constraint logic programming, CLP |
31 | Ana Belén Barragáns-Martínez, José Juan Pazos-Arias |
chi-SCTL/MUS: A Formal Methodology to Evolve Multi-Perspective Software Requirements Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 26th International Conference on Software Engineering (ICSE 2004), 23-28 May 2004, Edinburgh, United Kingdom, pp. 72-74, 2004, IEEE Computer Society, 0-7695-2163-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Requirements Refinement, Unspecification, Specification Evolution, Multi-Perspective Environment, Viewpoints, Inconsistency |
31 | José Juan Pazos-Arias, Jorge García Duque |
SCTL-MUS: A Formal Methodology for Software Development of Distributed Systems. A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Aspects Comput. ![In: Formal Aspects Comput. 13(1), pp. 50-91, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Incremental specification, Unspecification, Formal verification, Temporal logic, Formal description techniques, Functional requirements |
31 | José I. Acha, José L. Huertas |
On Input and Next-State Equations of the R-S Type M-Stable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 25(7), pp. 759-763, 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
Input equations, multistable circuits, next-state equation, partial unspecification, logic design, many-valued logic |
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