Search results for "VLD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
153	Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64.	FCCM	2002	DBLP DOI BibTeX RDF
124	Yanmei Qu, Shunliang Mei, Yun He	A Cost-effective VLD Architecture for MPEG-2 and AVS.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	CA-2D-VLC, VLD, inverse quantisation, MPEG-2, AVS, VLC
114	Tao Sheng, Mudar Sarem, Jingli Zhou	Memory Efficient and Low Complexity Variable Length Decoding for MPEG-4 Applications.	ICPP Workshops	2007	DBLP DOI BibTeX RDF
90	Yanmei Qu, Yun He, Shunliang Mei	A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	group-based VLD, VLSI, H.264/AVC, CAVLC
76	Zhidong Li, Evan Tan, J. Chen, Thanes Wassantachat	On Traffic Density Estimation with a Boosted SVM Classifier.	DICTA	2008	DBLP DOI BibTeX RDF
76	Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
57	Thanes Wassantachat, Zhidong Li, Jing Chen, Yang Wang 0002, Evan Tan	Traffic Density Estimation with On-line SVM Classifier.	AVSS	2009	DBLP DOI BibTeX RDF
57	Yong Ho Moon, Il Kyu Eom, Suk Woon Ha	An improved coeff_token variable length decoding mehod for low power design of H.264/AVC CAVLC decoder.	ICIP	2008	DBLP DOI BibTeX RDF
57	Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	Pel reconstruction on FPGA-augmented TriMedia.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
52	Wei Liu, Yong-en Chen	VLD Design for AVS Video Decoder.	WKDD	2009	DBLP DOI BibTeX RDF
52	Yanmei Qu, Yu Li, Shunliang Mei	A Cost-Effective VLSI Architecture of VLD for MPEG-2 and AVS.	ICME	2007	DBLP DOI BibTeX RDF
38	Chih-Da Chien, Keng-Po Lu, Yu-Min Chen, Jiun-In Guo, Yuan-Sun Chu, Ching-Lung Su	An Area-Efficient Variable Length Decoder IP Core Design for MPEG-1/2/4 Video Coding Applications.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
38	Mohanarajah Sinnathamby, Subramania Sudharsanan, Naraig Manjikian	Enhanced Architectural Support for Variable-Length Decoding.	ICME	2006	DBLP DOI BibTeX RDF
38	Xiaoming Bao, See-Kiong Ng, Eng-Huat Chua, Wei-Khing For	Virtual Lab Dashboard: Ubiquitous Monitoring and Control in a Smart Bio-laboratory.	ICCSA (2)	2005	DBLP DOI BibTeX RDF
38	Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha	Multiple-symbol parallel decoding for variable length codes.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
38	Matjaz Verderber, Andrej Zemva, Damjan Lampret	HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder.	DATE	2003	DBLP DOI BibTeX RDF
38	Matjaz Verderber, Andrej Zemva, Andrej Trost	HW/SW Codesign of the MPEG-2 Video Decoder.	IPDPS	2003	DBLP DOI BibTeX RDF
38	Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Mihai Sima, Petri Liuha	Parallel Multiple-Symbol Variable-Length Decoding.	ICCD	2002	DBLP DOI BibTeX RDF
38	Edgar Holmann, Toyohiko Yoshida, Akira Yamada 0005, Shin-ichi Uramoto	Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
33	Shuo Yang, Chunjuan Bo, Junxing Zhang, Pengxiang Gao, Yujie Li 0001, Seiichi Serikawa	VLD-45: A Big Dataset for Vehicle Logo Recognition and Detection.	IEEE Trans. Intell. Transp. Syst.	2022	DBLP DOI BibTeX RDF
33	Xiong Wang, Linghe Kong, Tianpeng Wei, Liang He 0002, Guihai Chen, Jiangtao Wang 0001, Chenren Xu	VLD: Smartphone-assisted Vertical Location Detection for Vehicles in Urban Environments.	IPSN	2020	DBLP DOI BibTeX RDF
33	Jun Liu, Xiaojun Jing, Songlin Sun, Zifeng Lian	Variable length dominant Gabor local binary pattern (VLD-GLBP) for face recognition.	VCIP	2014	DBLP DOI BibTeX RDF
33	Yutong Liu, Zhenqiang Yang, Huizhu Jia, Don Xie	A high speed and efficient architecture of VLD for AVS HD video decoder.	PCS	2012	DBLP DOI BibTeX RDF
33	Cesare Ronsisvalle, Vincenzo Enea	Improvement of high-voltage junction termination extension (JTE) by an optimized profile of lateral doping (VLD).	Microelectron. Reliab.	2010	DBLP DOI BibTeX RDF
33	Liang-Hao Wang, Dongxiao Li, Ming Zhang 0001	SoC Design of VLD in Multi-standard Video Decoder for Wearable Multimedia Players.	APWCS	2010	DBLP DOI BibTeX RDF	multi-standard, video, SoC, wearable system
33	Bin Sheng, Wen Gao 0001, Don Xie, Di Wu 0022	An efficient VLSI architecture of VLD for AVS HDTV decoder.	IEEE Trans. Consumer Electron.	2006	DBLP DOI BibTeX RDF
33	Cheng-Hung Liu, Bai-Jue Shieh, Chen-Yi Lee	A low-power group-based VLD design.	ISCAS (2)	2004	DBLP BibTeX RDF
19	Jianjun Li, Dandan Ding, Christophe Lucarz, Samuel Keller, Marco Mattavelli	Efficient data flow variable length decoding implementation for the MPEG reconfigurable video coding framework.	SiPS	2008	DBLP DOI BibTeX RDF
19	Lei Yang 0050, Xiaowei Song 0001, Chunping Hou, Jufeng Dai	A Scheme for MPEG-2 to H.264 Transcoding.	CCECE	2006	DBLP DOI BibTeX RDF
19	Ganesh Yadav, R. K. Singh, Vipin Chaudhary	On Implementation of MPEG-2 Like Real-Time Parallel Media Applications on MDSP SoC Cradle Architecture.	EUC	2004	DBLP DOI BibTeX RDF
19	Lingfeng Li, Danian Gong, Yun He	A single-chip real-time programmable video signal processor.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
19	Seong-Hwan Cho, Thucydides Xanthopoulos, Anantha P. Chandrakasan	A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF