Search results for "XOR-gate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
62	Yibin Ye, Kaushik Roy 0001, Rolf Drechsler	Power Consumption in XOR-Based Circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
50	Yinshui Xia, A. E. A. Almaini	Best Polarity for Low Power XOR Gate Decomposition.	DSD	2002	DBLP DOI BibTeX RDF
40	Hamed F. Dadgour, Muhammad Mustafa Hussain, Casey Smith, Kaustav Banerjee	Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS.	DAC	2010	DBLP DOI BibTeX RDF	energy-efficient electronics, laterally-actuated NEMS, nano-electro-mechanical switches, steep-subthreshold switch, logic design, process variation
35	Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee	Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	AOP, finite field, Bit-parallel systolic multiplier, ESP
32	Hai Zhou 0001, D. F. Wong 0001	Optimal low power X OR gate decomposition.	DAC	2000	DBLP DOI BibTeX RDF
29	Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan	A linear code-preserving signature analyzer COPMISR.	VTS	1997	DBLP DOI BibTeX RDF	linear separable code, code preserving multi-input signature register, COPMISR, concurrent checking, parity code, group -parity code, BIST, linear codes, Hamming code, duplication code, XOR-gate, signature analyzer, on-line error detection
27	Geoff V. Merrett, Bashir M. Al-Hashimi	Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.	PATMOS	2004	DBLP DOI BibTeX RDF
27	Chiou-Yng Lee, Ya-Cheng Lu, Erl-Huei Lu	Low-complexity systolic multiplier over GF(2m) using weakly dual basis.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
27	Dimitris Nikolos	Self-Testing Embedded Two-Rail Checkers.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	parity tree, embedded self-testing, self testing, two-rail checker, parity checker
24	Xiaoxuan Peng, Xiaohu Ge, Yajun Ha	Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
24	Mrinal Goswami, Avayjeet Paul, Arpita Nath Boruah	Zero Logic Based Stable Three Input QCA XOR Gate.	ASCAT	2024	DBLP DOI BibTeX RDF
24	Uma Sharma, Mansi Jhamb	Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
24	Seyed-Sajad Ahmadpour, Nima Jafari Navimipour, Mohammad Mosleh, Ali Newaz Bahar, Senay Yalçin	A nano-scale n-bit ripple carry adder using an optimized XOR gate and quantum-dots technology with diminished cells and power dissipation.	Nano Commun. Networks	2023	DBLP DOI BibTeX RDF
24	András Horváth, Alon Ascoli, Ronald Tetzlaff	Implementation of the XOR gate with two memristive neurons.	MOCAST	2023	DBLP DOI BibTeX RDF
24	Ali H. Majeed, Esam Alkaldy	High-performance adder using a new XOR gate in QCA technology.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
24	Rithambara Shivraj Singh Rajput, Sujata Nandeshwar Patil	90 nm CMOS Implementation of Multiplicative Inverse of the S-Box for AES Algorithm Using Six Transistor XOR Gate.	Int. J. e Collab.	2022	DBLP DOI BibTeX RDF
24	Syed Farah Naz, Sajid Khan 0001, Ambika Prasad Shah	Pass Transistor XOR Gate Based Radiation Hardened RO-PUF.	VDAT	2022	DBLP DOI BibTeX RDF
24	Ashif Raja, Kousik Mukherjee, J. N. Roy	Analysis of new all optical polarization-encoded Dual SOA-based ternary NOT & XOR gate with simulation.	Photonic Netw. Commun.	2021	DBLP DOI BibTeX RDF
24	Syed Farah Naz, Ambika Prasad Shah, Suhaib Ahmed, Patrick Girard 0001, Michael Waltl	Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata.	ETS	2021	DBLP DOI BibTeX RDF
24	Ki Beom Lee, Sumin Lee, Sunghwan Joo, Hong Keun Ahn, Young Seok Jung, Seong-Ook Jung	CNN encryption using XOR Gate for Hardware Optimization.	ISOCC	2021	DBLP DOI BibTeX RDF
24	Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa	An efficient Design of three-input XOR gate in QCA technology.	SSD	2021	DBLP DOI BibTeX RDF
24	Katsuhiro Nishijima, Takashi Nakakuki	XOR Gate Design Toward a Practical Complete Set for DNA Computing.	New Gener. Comput.	2020	DBLP DOI BibTeX RDF
24	Amer Kotb, Kyriakos E. Zoiros, Chunlei Guo	320 Gb/s all-optical XOR gate using semiconductor optical amplifier-Mach-Zehnder interferometer and delayed interferometer.	Photonic Netw. Commun.	2019	DBLP DOI BibTeX RDF
24	Sen Wang, Ying Yang, Wenbin Song, Huanqing Cui, Cheng Li, Li Cai	All-spin logic XOR gate implementation based on input interface.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
24	Hossein Mohammadi, Keivan Navi	Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
24	Jerzy Gorecki, Hiroyuki Kitahata, Yuki Koyano, Marian Gryciuk, Maciej Malecki, Nobuhiko J. Suematsu	XOR Gate for Information Coded with Camphor Particles Moving on the Water Surface.	Int. J. Unconv. Comput.	2017	DBLP BibTeX RDF
24	Hua Chen, Guiliang Guo, Qiangtao Lai, Yulin Zhang, Jingyu Han, Yuepeng Yan	0.3-4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
24	Enaul haq Shaik, Nakkeeran Rangaswamy	High contrast all-optical XOR gate with T-shaped photonic crystal waveguide using phase based interference.	WOCN	2017	DBLP DOI BibTeX RDF
24	Lei Zhang 0089, Chenghua Wang, Weiqiang Liu 0001, Máire O'Neill, Fabrizio Lombardi	XOR gate based low-cost configurable RO PUF.	ISCAS	2017	DBLP DOI BibTeX RDF
24	Ahmed S. Emara, Ahmed H. Madian, Hassanein H. Amer, S. H. Amer, Mohamed B. Abdelhalim	Testing of memristor ratioed logic (MRL) XOR gate.	ICM	2016	DBLP DOI BibTeX RDF
24	Savas Konur, Marian Gheorghe 0001, Ciprian Dragomir, Florentin Ipate, Natalio Krasnogor	Conventional Verification for Unconventional Computing: a Genetic XOR Gate Example.	Fundam. Informaticae	2014	DBLP DOI BibTeX RDF
24	Nabihah Ahmad, S. M. Rezaul Hasan	Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate.	Integr.	2013	DBLP DOI BibTeX RDF
24	Salvador Manich, Martin Strasser	A Highly Time Sensitive XOR Gate for Probe Attempt Detectors.	IEEE Trans. Circuits Syst. II Express Briefs	2013	DBLP DOI BibTeX RDF
24	Manoj Sharma, Arti Noor	CPL-Adiabatic Gated logic (CPLAG) XOR gate.	ICACCI	2013	DBLP DOI BibTeX RDF
24	Emma Lazzeri, Antonio Malacarne, Giovanni Serafino, Antonella Bogoni	All-Optical XOR Gate for QPSK In-Phase and Quadrature Components Based on Periodically Poled Lithium Niobate Waveguide for Photonic Coding and Error Detection Applications.	OSC	2012	DBLP DOI BibTeX RDF
24	Jan Halamek, Vera Bocharova, Mary A. Arugula, Guinevere Strack, Vladimir Privman, Evgeny Katz	Realization and Properties of Biochemical-Computing Biocatalytic XOR Gate Based on Enzyme Inhibition by a Substrate	CoRR	2011	DBLP BibTeX RDF
24	Jared Tessier, Randa Ayoubi, Magdy A. Bayoumi	Energy-efficient XOR gate with embedded level conversion for serial-link encoding.	SiPS	2011	DBLP DOI BibTeX RDF
24	Jeffrey Ventrella	A Spherical XOR Gate Implemented in the Game of Life.	Game of Life Cellular Automata	2010	DBLP DOI BibTeX RDF
24	Kyriakos E. Zoiros, Thanassis Siarkos	Design rules for full pattern-operated all-optical XOR gate with single semiconductor optical amplifier-based ultrafast nonlinear interferometer.	CSNDSP	2010	DBLP DOI BibTeX RDF
22	Silvia Ferrari, Bhavesh Mehta, Gianluca Di Muro, Antonius M. J. VanDongen, Craig Henriquez	Biologically realizable reward-modulated hebbian training for spiking neural networks.	IJCNN	2008	DBLP DOI BibTeX RDF
22	Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin	Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m).	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	cryptography, fault-tolerant computing, fault detection, multiplier, finite fields arithmetic
22	P. Zhongliang	Testable Realizations for ESOP Expressions of Logic Functions.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
18	Chiou-Yng Lee, Che Wun Chiou	New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	finite field, normal basis, polynomial basis, bit-parallel systolic multiplier
18	Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.	A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	3:2 counter, 4:2 compressor, 5:3 compressor, 5:2 compressor, MAC, multiplier
13	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.	VLSI Design	2007	DBLP DOI BibTeX RDF
13	Sun-Mi Park, Ku-Young Chang, Dowon Hong	Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	shifted polynomial basis, irreducible pentanomial, finite field arithmetic, Bit-parallel multiplier
13	Yuxiang Zheng, Jiang Li, Jin Liu, Qian Yu	Automatic within-pair-skew compensation for 6.25 Gbps differential links using wide-bandwidth delay units.	ISCAS	2006	DBLP DOI BibTeX RDF
13	Dilip V. Sarwate, Naresh R. Shanbhag	High-speed architectures for Reed-Solomon decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
13	Hong-Yi Huang, Teng-Neng Wang	High-speed CMOS logic circuits in capacitor coupling technique.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
13	Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer	Automated synthesis of phase shifters for built-in self-testapplications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
13	Hanan A. Mahmoud, Magdy A. Bayoumi	A 10-transistor low-power high-speed full adder cell.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
13	Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer	Automated synthesis of large phase shifters for built-in self-test.	ITC	1998	DBLP DOI BibTeX RDF
13	Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta 0002, Melvin A. Breuer	An integrated system for assigning signal flow directions to CMOS transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF