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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 29 occurrences of 25 keywords
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Results
Found 53 publication records. Showing 53 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
62 | Yibin Ye, Kaushik Roy 0001, Rolf Drechsler |
Power Consumption in XOR-Based Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 299-302, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
50 | Yinshui Xia, A. E. A. Almaini |
Best Polarity for Low Power XOR Gate Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 53-59, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Hamed F. Dadgour, Muhammad Mustafa Hussain, Casey Smith, Kaustav Banerjee |
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 893-896, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
energy-efficient electronics, laterally-actuated NEMS, nano-electro-mechanical switches, steep-subthreshold switch, logic design, process variation |
35 | Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee |
Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(5), pp. 385-393, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
AOP, finite field, Bit-parallel systolic multiplier, ESP |
32 | Hai Zhou 0001, D. F. Wong 0001 |
Optimal low power X OR gate decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 104-107, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan |
A linear code-preserving signature analyzer COPMISR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 350-355, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
linear separable code, code preserving multi-input signature register, COPMISR, concurrent checking, parity code, group -parity code, BIST, linear codes, Hamming code, duplication code, XOR-gate, signature analyzer, on-line error detection |
27 | Geoff V. Merrett, Bashir M. Al-Hashimi |
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 198-207, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Chiou-Yng Lee, Ya-Cheng Lu, Erl-Huei Lu |
Low-complexity systolic multiplier over GF(2m) using weakly dual basis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 367-372, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Dimitris Nikolos |
Self-Testing Embedded Two-Rail Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 69-79, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
parity tree, embedded self-testing, self testing, two-rail checker, parity checker |
24 | Xiaoxuan Peng, Xiaohu Ge, Yajun Ha |
Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(1), pp. 348-358, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Mrinal Goswami, Avayjeet Paul, Arpita Nath Boruah |
Zero Logic Based Stable Three Input QCA XOR Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASCAT ![In: Cellular Automata Technology - Third Asian Symposium, ASCAT 2024, Durgapur, India, February 29 - March 2, 2024, Revised Selected Papers, pp. 99-108, 2024, Springer, 978-3-031-56942-5. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
24 | Uma Sharma, Mansi Jhamb |
Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(5), pp. 2852-2871, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Seyed-Sajad Ahmadpour, Nima Jafari Navimipour, Mohammad Mosleh, Ali Newaz Bahar, Senay Yalçin |
A nano-scale n-bit ripple carry adder using an optimized XOR gate and quantum-dots technology with diminished cells and power dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nano Commun. Networks ![In: Nano Commun. Networks 36, pp. 100442, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | András Horváth, Alon Ascoli, Ronald Tetzlaff |
Implementation of the XOR gate with two memristive neurons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 12th International Conference on Modern Circuits and Systems Technologies, MOCAST 2023, Athens, Greece, June 28-30, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-2107-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Ali H. Majeed, Esam Alkaldy |
High-performance adder using a new XOR gate in QCA technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 78(9), pp. 11564-11579, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Rithambara Shivraj Singh Rajput, Sujata Nandeshwar Patil |
90 nm CMOS Implementation of Multiplicative Inverse of the S-Box for AES Algorithm Using Six Transistor XOR Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. e Collab. ![In: Int. J. e Collab. 18(1), pp. 1-16, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Syed Farah Naz, Sajid Khan 0001, Ambika Prasad Shah |
Pass Transistor XOR Gate Based Radiation Hardened RO-PUF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 331-344, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Ashif Raja, Kousik Mukherjee, J. N. Roy |
Analysis of new all optical polarization-encoded Dual SOA-based ternary NOT & XOR gate with simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 41(3), pp. 242-251, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Syed Farah Naz, Ambika Prasad Shah, Suhaib Ahmed, Patrick Girard 0001, Michael Waltl |
Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 26th IEEE European Test Symposium, ETS 2021, Bruges, Belgium, May 24-28, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-1849-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Ki Beom Lee, Sumin Lee, Sunghwan Joo, Hong Keun Ahn, Young Seok Jung, Seong-Ook Jung |
CNN encryption using XOR Gate for Hardware Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 359-360, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa |
An efficient Design of three-input XOR gate in QCA technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSD ![In: 18th International Multi-Conference on Systems, Signals & Devices, SSD 2021, Monastir, Tunisia, March 22-25, 2021, pp. 1172-1176, 2021, IEEE, 978-1-6654-1493-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Katsuhiro Nishijima, Takashi Nakakuki |
XOR Gate Design Toward a Practical Complete Set for DNA Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
New Gener. Comput. ![In: New Gener. Comput. 38(2), pp. 285-301, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Amer Kotb, Kyriakos E. Zoiros, Chunlei Guo |
320 Gb/s all-optical XOR gate using semiconductor optical amplifier-Mach-Zehnder interferometer and delayed interferometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 38(1), pp. 177-184, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Sen Wang, Ying Yang, Wenbin Song, Huanqing Cui, Cheng Li, Li Cai |
All-spin logic XOR gate implementation based on input interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(5), pp. 607-613, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Hossein Mohammadi, Keivan Navi |
Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 27(14), pp. 1850216:1-1850216:19, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Jerzy Gorecki, Hiroyuki Kitahata, Yuki Koyano, Marian Gryciuk, Maciej Malecki, Nobuhiko J. Suematsu |
XOR Gate for Information Coded with Camphor Particles Moving on the Water Surface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Unconv. Comput. ![In: Int. J. Unconv. Comput. 13(6), pp. 417-434, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
24 | Hua Chen, Guiliang Guo, Qiangtao Lai, Yulin Zhang, Jingyu Han, Yuepeng Yan |
0.3-4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 14(12), pp. 20170450, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Enaul haq Shaik, Nakkeeran Rangaswamy |
High contrast all-optical XOR gate with T-shaped photonic crystal waveguide using phase based interference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOCN ![In: Fourteenth International Conference on Wireless and Optical Communications Networks, WOCN 2017, Mumbai, India, February 24-26, 2017, pp. 1-3, 2017, IEEE, 978-1-5090-4884-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Lei Zhang 0089, Chenghua Wang, Weiqiang Liu 0001, Máire O'Neill, Fabrizio Lombardi |
XOR gate based low-cost configurable RO PUF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Ahmed S. Emara, Ahmed H. Madian, Hassanein H. Amer, S. H. Amer, Mohamed B. Abdelhalim |
Testing of memristor ratioed logic (MRL) XOR gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 28th International Conference on Microelectronics, ICM 2016, Giza, Egypt, December 17-20, 2016, pp. 181-184, 2016, IEEE, 978-1-5090-5721-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Savas Konur, Marian Gheorghe 0001, Ciprian Dragomir, Florentin Ipate, Natalio Krasnogor |
Conventional Verification for Unconventional Computing: a Genetic XOR Gate Example. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fundam. Informaticae ![In: Fundam. Informaticae 134(1-2), pp. 97-110, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Nabihah Ahmad, S. M. Rezaul Hasan |
Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 46(4), pp. 333-344, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Salvador Manich, Martin Strasser |
A Highly Time Sensitive XOR Gate for Probe Attempt Detectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 60-II(11), pp. 786-790, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Manoj Sharma, Arti Noor |
CPL-Adiabatic Gated logic (CPLAG) XOR gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: International Conference on Advances in Computing, Communications and Informatics, ICACCI 2013, Mysore, India, August 22-25, 2013, pp. 575-579, 2013, IEEE, 978-1-4799-2432-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Emma Lazzeri, Antonio Malacarne, Giovanni Serafino, Antonella Bogoni |
All-Optical XOR Gate for QPSK In-Phase and Quadrature Components Based on Periodically Poled Lithium Niobate Waveguide for Photonic Coding and Error Detection Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OSC ![In: Optical Supercomputing - 4th International Workshop, OSC 2012, in Memory of H. John Caulfield, Bertinoro, Italy, July 19-21, 2012. Revised Selected Papers, pp. 35-41, 2012, Springer, 978-3-642-38249-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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24 | Jan Halamek, Vera Bocharova, Mary A. Arugula, Guinevere Strack, Vladimir Privman, Evgeny Katz |
Realization and Properties of Biochemical-Computing Biocatalytic XOR Gate Based on Enzyme Inhibition by a Substrate ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1105.4927, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
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24 | Jared Tessier, Randa Ayoubi, Magdy A. Bayoumi |
Energy-efficient XOR gate with embedded level conversion for serial-link encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2011, October 4-7, 2011, Beirut, Lebanon, pp. 140-145, 2011, IEEE, 978-1-4577-1920-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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24 | Jeffrey Ventrella |
A Spherical XOR Gate Implemented in the Game of Life. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Game of Life Cellular Automata ![In: Game of Life Cellular Automata., pp. 379-385, 2010, Springer, 978-1-8499-6216-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Kyriakos E. Zoiros, Thanassis Siarkos |
Design rules for full pattern-operated all-optical XOR gate with single semiconductor optical amplifier-based ultrafast nonlinear interferometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSNDSP ![In: Proceedings of the 7th International Symposium on Communication Systems Networks and Digital Signal Processing, CSNDSP 2010, University of Northumbria at Newcastle, UK, 21-23 July 2010, pp. 631-635, 2010, IEEE, 978-1-86135-369-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
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22 | Silvia Ferrari, Bhavesh Mehta, Gianluca Di Muro, Antonius M. J. VanDongen, Craig Henriquez |
Biologically realizable reward-modulated hebbian training for spiking neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2008, part of the IEEE World Congress on Computational Intelligence, WCCI 2008, Hong Kong, China, June 1-6, 2008, pp. 1780-1786, 2008, IEEE, 978-1-4244-1820-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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22 | Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin |
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 143-150, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
cryptography, fault-tolerant computing, fault detection, multiplier, finite fields arithmetic |
22 | P. Zhongliang |
Testable Realizations for ESOP Expressions of Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 140-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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18 | Chiou-Yng Lee, Che Wun Chiou |
New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 313-324, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
finite field, normal basis, polynomial basis, bit-parallel systolic multiplier |
18 | Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr. |
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(2), pp. 77-89, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
3:2 counter, 4:2 compressor, 5:3 compressor, 5:2 compressor, MAC, multiplier |
13 | Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas |
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 324-329, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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13 | Sun-Mi Park, Ku-Young Chang, Dowon Hong |
Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(9), pp. 1211-1215, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
shifted polynomial basis, irreducible pentanomial, finite field arithmetic, Bit-parallel multiplier |
13 | Yuxiang Zheng, Jiang Li, Jin Liu, Qian Yu |
Automatic within-pair-skew compensation for 6.25 Gbps differential links using wide-bandwidth delay units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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13 | Dilip V. Sarwate, Naresh R. Shanbhag |
High-speed architectures for Reed-Solomon decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(5), pp. 641-655, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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13 | Hong-Yi Huang, Teng-Neng Wang |
High-speed CMOS logic circuits in capacitor coupling technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 634-637, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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13 | Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer |
Automated synthesis of phase shifters for built-in self-testapplications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10), pp. 1175-1188, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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13 | Hanan A. Mahmoud, Magdy A. Bayoumi |
A 10-transistor low-power high-speed full adder cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 43-46, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
13 | Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer |
Automated synthesis of large phase shifters for built-in self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1047-1056, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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13 | Kuen-Jong Lee, Chih-Nan Wang, Rajiv Gupta 0002, Melvin A. Breuer |
An integrated system for assigning signal flow directions to CMOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1445-1458, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
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