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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 685 occurrences of 426 keywords
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Results
Found 3067 publication records. Showing 3067 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
97 | Eric William Burger, Guido Dedene |
Economics of point accelleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 424-428, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
CAD Development Methodology, Economics of CAD Systems, Routing Accelerators, Total CAD Systems, Logic Synthesis, Simulation Accelerators |
90 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 335-342, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
extensible embedded processor, reconfigurable computing, kernel, accelerator, replacement, run-time adaptation |
80 | Amir Hormati, Nathan Clark, Scott A. Mahlke |
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Fifth International Symposium on Code Generation and Optimization (CGO 2007), 11-14 March 2007, San Jose, California, USA, pp. 341-353, 2007, IEEE Computer Society, 978-0-7695-2764-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
80 | Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke |
Increasing hardware efficiency with multifunction loop accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 276-281, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware |
70 | Sébastien Lafond, Johan Lilius |
Interrupt Costs in Embedded System with Short Latency Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 15th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2008), 31 March - 4 April 2008, Belfast, Northern Ireland, pp. 317-325, 2008, IEEE Computer Society, 978-0-7695-3141-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Interrupt, Hardware accelerator |
61 | Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao |
Dynamically utilizing computation accelerators for extensible processors in a software approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 51-60, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
computation accelerator, ASIP, dynamic binary translation |
61 | Sami Yehia, Nathan Clark, Scott A. Mahlke, Krisztián Flautner |
Exploring the design space of LUT-based transparent accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 11-21, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
accelerator design, embedded processing, efficient computation |
58 | Sean Rul, Hans Vandierendonck, Koen De Bosschere |
Towards automatic program partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 89-98, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
off-loading, sub-algorithms, partitioning, accelerators |
58 | Jeff H. Derby, Robert K. Montoye, José E. Moreira |
VICTORIA: VMX indirect compute technology oriented towards in-line acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 303-312, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
VMX, SIMD, accelerators, powerPC |
54 | Samuel Williams 0001, Nathan Bell, Jee Whan Choi, Michael Garland, Leonid Oliker, Richard Vu |
Sparse Matrix-Vector Multiplication on Multicore and Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 83-109, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
54 | Kaushik Datta, Samuel Williams 0001, Vasily Volkov, Jonathan Carter, Leonid Oliker, John Shalf, Katherine A. Yelick |
Auto-Tuning Stencil Computations on Multicore and Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 219-253, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
51 | John H. Kelm, Steven S. Lumetta |
HybridOS: runtime support for reconfigurable accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 212-221, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CPU/accelerator architecture, operating system, reconfigurable computing |
51 | Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier |
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | José Carlos Sancho, Darren J. Kerbyson |
Dynamic Load Balancing of Matrix-Vector Multiplications on Roadrunner Compute Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. Proceedings, pp. 166-177, 2009, Springer, 978-3-642-03868-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
49 | Nathan Clark, Amir Hormati, Sami Yehia, Scott A. Mahlke, Krisztián Flautner |
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 216-227, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Manjunath Kudlur, Kevin Fan, Scott A. Mahlke |
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 270-275, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
system-level synthesis, loop accelerator, application-specific hardware |
42 | Hari Subramoni, Fabrizio Petrini, Virat Agarwal, Davide Pasetto |
High Performance Topology-Aware Communication in Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 443-460, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Cecilia González-Alvarez, Harald Servat, Daniel Cabrera-Benitez, Xavier Aguilar, Carles Pons, Juan Fernández-Recio, Daniel Jiménez-González |
Drug Design on the Cell BE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 331-350, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Ümit V. Çatalyürek, Renato Ferreira 0001, Timothy D. R. Hartley, George Teodoro, Rafael Sachetto Oliveira |
Data Flow Frameworks for Emerging Heterogeneous Architectures and Their Application to Biomedicine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 375-392, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Dominik Göddeke, Robert Strzodka |
Mixed-Precision GPU-Multigrid Solvers with Strong Smoothers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 131-147, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Stefan Turek, Dominik Göddeke, Sven H. M. Buijssen, Hilmar Wobker |
Hardware-Oriented Multigrid Finite Element Solvers on GPU-Accelerated Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 113-130, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Matthias Christen, Olaf Schenk, Esra Neufeld, Maarten M. Paulides, Helmar Burkhart |
Manycore Stencil Computations in Hyperthermia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 255-277, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Alex Chung Hen Chow, Gordon C. Fossum, Daniel A. Brokenshire |
Implementing FFTs on Multicore Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 171-192, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Jakub Kurzak, Jack J. Dongarra |
Implementing Matrix Factorizations on the Cell B. E. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 21-35, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Wesley Alvaro, Jakub Kurzak, Jack J. Dongarra |
Implementing Matrix Multiplication on the Cell B. E. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 3-20, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | David A. Bader, Virat Agarwal, Kamesh Madduri, Fabrizio Petrini |
Combinatorial Algorithm Design on the Cell/B.E. Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 195-216, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Rajib Nath, Stanimire Tomov, Jack J. Dongarra |
BLAS for GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 57-80, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Laxmikant V. Kalé, David M. Kunzman, Lukasz Wesolowski |
Accelerator Support in the Charm++ Parallel Programming Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 393-411, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Abhinav Sarje, Jaroslaw Zola, Srinivas Aluru |
Pairwise Computations on the Cell Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 297-327, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Stanimire Tomov, Jack J. Dongarra |
Dense Linear Algebra for Hybrid GPU-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 37-55, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Vipin Sachdeva, Michael Kistler, Tzy-Hwa Kathy Tzeng |
Enabling Bioinformatics Algorithms on the Cell/B.E. Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 281-296, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Shubhabrata Sengupta, Mark J. Harris, Michael Garland, John D. Owens |
Efficient Parallel Scan Algorithms for Manycore GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 413-442, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Virat Agarwal, David A. Bader |
Designing Fast Fourier Transform for the IBM Cell Broadband Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 151-170, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
42 | John E. Stone, David J. Hardy, Barry Isralewitz, Klaus Schulten |
GPU Algorithms for Molecular Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Scientific Computing with Multicore and Accelerators ![In: Scientific Computing with Multicore and Accelerators., pp. 351-371, 2010, CRC Press / Taylor & Francis, 978-1-4398-2536-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
41 | Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silvén |
Programmable Accelerators for Reconfigurable Video Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 36-47, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull |
DVFS in loop accelerators using BLADES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 894-897, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded systems, low power, high-level synthesis, voltage scaling, frequency scaling |
41 | Walid A. Najjar |
Compiling code accelerators for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 1-2, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA code acceleration |
41 | Nathan Clark, Amir Hormati, Scott A. Mahlke, Sami Yehia |
Scalable subgraph mapping for acyclic computation accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 147-157, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
compilation, embedded processors |
40 | Michael Kistler, John A. Gunnels, Daniel A. Brokenshire, Brad Benton |
Petascale computing with accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 241-250, 2009, ACM, 978-1-60558-397-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
hybrid programming models, accelerators |
40 | Lech Józwiak, Alexander Douglas |
Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 1123-1130, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
re-configurable computing, heterogeneous pipelined accelerators, hardware synthesis, EDA-tool |
40 | Reiner W. Hartenstein, Jürgen Becker 0001 |
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 146-150, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
data-driven Xputer-based accelerators, CoDe-X, profiling-driven host/accelerator partitioning, resource-driven sequential/structural partitioning, accelerator source code, reconfigurable resources, C dialect, data-procedural language features, parallel programming, partitioning, performance optimization, hardware/software co-design, parallelizing programming environment |
40 | Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man |
Synthesis of pipelined DSP accelerators with dynamic scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 72-77, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules |
39 | Evangelos Vlachos, Michelle L. Goodstein, Michael A. Kozuch, Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry |
ParaLog: enabling and accelerating online parallel monitoring of multithreaded applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 271-284, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
hardware support for debugging, instruction-grain lifeguards, online parallel monitoring |
39 | Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich |
Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 161-168, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Nagaraju Pothineni, Anshul Kumar, Kolin Paul |
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 261-266, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid |
Two-level microprocessor-accelerator partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 313-318, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Ajay V. Bhatt |
The Intel Geneseo Project. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 1, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Wei Wang, Qiang Wu, Wei Xie |
Hardware-Software Co-design for Dynamic Reconfigurable Computing with Collaborative Supports of Architecture and Operating System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCWD ![In: Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, CSCWD 2007, April 26-28, 2007, Melbourne, Australia, pp. 275-279, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta |
High-performance, energy-efficient platforms using in-socket FPGA accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 261-264, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
in-socket accelerator, fpga, agility |
31 | Andreas Heinig, Jochen Strunk, Wolfgang Rehm, Heiko Schick |
ACCFS - Operating System Integration of Computational Accelerators Using a VFS Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 374-379, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Filip Blagojevic, Costin Iancu, Katherine A. Yelick, Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Benjamin Rose |
Scheduling dynamic parallelism on accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 161-170, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cooperative scheduling, cell be |
31 | Toshio Endo, Satoshi Matsuoka |
Massive supercomputing coping with heterogeneity of modern accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-10, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Zdenek Vasícek, Lukás Sekanina |
Hardware Accelerators for Cartesian Genetic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroGP ![In: Genetic Programming, 11th European Conference, EuroGP 2008, Naples, Italy, March 26-28, 2008. Proceedings, pp. 230-241, 2008, Springer, 978-3-540-78670-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Ya-Shuai Lü, Li Shen 0007, Libo Huang, Zhiying Wang 0003, Nong Xiao |
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 197-200, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
subgraph covering, VLIW, ASIPs, extensible processors |
31 | Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas |
Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman |
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 31(2), pp. 127-142, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
high-level hardware synthesis, automatic parallelization, datapath synthesis |
31 | Ricardo A. Fonseca, Luís O. Silva, Frank S. Tsung, Viktor K. Decyk, Wei Lu 0029, Chuang Ren, Warren B. Mori, S. Deng, S. Lee, Thomas C. Katsouleas, J. C. Adam |
OSIRIS: A Three-Dimensional, Fully Relativistic Particle in Cell Code for Modeling Plasma Based Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (3) ![In: Computational Science - ICCS 2002, International Conference, Amsterdam, The Netherlands, April 21-24, 2002. Proceedings, Part III, pp. 342-351, 2002, Springer, 3-540-43594-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Andreas Adelmann, Derek Feichtinger |
Generic Large Scale 3D Visualization of Accelerators and Beam Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (3) ![In: Computational Science - ICCS 2002, International Conference, Amsterdam, The Netherlands, April 21-24, 2002. Proceedings, Part III, pp. 362-371, 2002, Springer, 3-540-43594-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Kenneth J. Turner, Qian Bing |
Protocol Techniques for Testing Radiotherapy Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORTE ![In: Formal Techniques for Networked and Distributed Systems - FORTE 2002, 22nd IFIP WG 6.1 International Conference Houston, Texas, USA, November 11-14, 2002, Proceedings, pp. 81-96, 2002, Springer, 3-540-00141-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | James J. Feenan Jr., Patrick Fry, Ming Lei |
Clustering Web Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WECWIS ![In: Fourth IEEE International Workshop on Advanced Issues of E-Commerce and Web-Based Information Systems (WECWIS'02), Newport Beach, California, USA, June 26-28, 2002, pp. 165-170, 2002, IEEE Computer Society, 0-7695-1567-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider |
High-Level Synthesis of Nonprogrammable Hardware Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 113-, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Reiner W. Hartenstein, Jürgen Becker 0001 |
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Fifth International Workshop on Hardware/Software Codesign, CODES/CASHE 1997, March 24-26, 1997, Braunschweig, Germany, pp. 141-145, 1997, IEEE Computer Society, 0-8186-7895-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
structural programmable co-processors, design space exploration, performance estimation |
31 | Volodymyr V. Kindratenko, Robert B. Wilhelmson, Robert J. Brunner, Todd J. Martínez, Wen-mei W. Hwu |
High-Performance Computing with Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Sci. Eng. ![In: Comput. Sci. Eng. 12(4), pp. 12-16, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
OpenMM, GPU, high-performance computing, OpenMP, accelerators |
31 | Lech Józwiak, Yahya Jan |
Architecture Design of Reconfigurable Accelerators for Demanding Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Seventh International Conference on Information Technology: New Generations, ITNG 2010, Las Vegas, Nevada, USA, 12-14 April 2010, pp. 1201-1206, 2010, IEEE Computer Society, 978-0-7695-3984-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reconfigurable accelerators, advanced applications, design-space exploration, architecture design |
31 | Rishiyur S. Nikhil |
Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design). ![Search on Bibsonomy](Pics/bibsonomy.png) |
GPCE ![In: Generative Programming and Component Engineering, 8th International Conference, GPCE 2009, Denver, Colorado, USA, October 4-5, 2009, Proceedings, pp. 1-2, 2009, ACM, 978-1-60558-494-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing |
31 | Karl M. Sammut, S. R. Jones |
Arithmetic Unit Design for Neural Accelerators: Cost Performance Issues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(10), pp. 1256-1260, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
linear array accelerators, arithmetic constructs, instruction set measurements, cost/performance trade-offs, Neural networks |
29 | Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier Temam |
Reconciling specialization and flexibility through compound circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 277-288, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Tomoaki Hamano, Toshio Endo, Satoshi Matsuoka |
Power-aware dynamic task scheduling for heterogeneous accelerated clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Sebastian Hessel, David Szczesny, Shadi Traboulsi, Attila Bilgic, Josef Hausner |
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 1-8, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Michael Gschwind |
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 478-485, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Jiri Kadlec, Roman Bartosinski, Martin Danek |
Accelerating Microblaze Floating Point Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 621-624, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Josh Harr |
Innovative technologies II - Multi-paradigm computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 282, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Robert D. Ryne |
High energy physics - 25 years of accelerator modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 60, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Nathan Clark, Jason A. Blome, Michael L. Chu, Scott A. Mahlke, Stuart Biles, Krisztián Flautner |
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 272-283, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood |
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11), pp. 1355-1371, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | L. Louis Zhang, Qiang Wang, David M. Lewis |
Design of a VLIW Compute Accelerator on the Transmogrifier-2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 3-12, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Yahya Jan, Lech Józwiak |
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 24-35, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC |
29 | Vikas Aggarwal, Rafael García, Greg Stitt, Alan D. George, Herman Lam |
SCF: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPRCTA@SC ![In: Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications, HPRTCA 2009, November 15, 2009, Portland, Oregon, USA, pp. 19-28, 2009, ACM, 978-1-60558-721-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
communication, coordination, reconfigurable computing, productivity, portability, heterogeneous computing, accelerators |
29 | Charles F. Webb |
IBM z10: The Next-Generation Mainframe Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 28(2), pp. 19-29, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
high-frequency design, decimal floating-point, reliability, pipeline, microprocessor, branch prediction, accelerators, symmetric multiprocessor (SMP), mainframe, Hot Chips 19 |
29 | Maurizio Paganini |
Nomadik®: A Mobile Multimedia Application Processor Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 749-750, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mobile multimedia application processor platform, Nomadik platform, industry standard host processor, low-power DSP, hardware accelerators |
29 | Pradip Bose |
Presilicon modeling: challenges in the late CMOS era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 25(4), pp. 5-6, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Integrated microarchitectures, special purpose accelerators, scalable on-chip interconnection network, presilicon modeling, CMOS |
29 | Charlie Johnson, Jeff Welser |
Future processors: flexible and modular. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 4-6, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multiprocessor, SoC, accelerators |
29 | Alberto Ferrante, Vincenzo Piuri, Fabien Castanier |
A QoS-enabled packet scheduling algorithm for IPSec multi-accelerator based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 221-229, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cryptographic accelerators, scheduling, QoS, quality of service, IPSec |
29 | Emil Jovanov, Veljko M. Milutinovic, Ali R. Hurson |
Acceleration of Nonnumeric Operations Using Hardware Support for the Ordered Table Hashing Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(9), pp. 1026-1040, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
nonnumeric processing, searching, sorting, hashing, hardware accelerators, Database operations |
23 | Md. Ashraful Islam, Kenji Kise |
Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HEART ![In: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2023, Kusatsu, Japan, June 14-16, 2023, pp. 78-85, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Christian Maximilian Karle, Marius Kreutzer, Johannes Pfau, Jürgen Becker 0001 |
A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HEART ![In: HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9 - 10, 2022, pp. 33-41, 2022, ACM, 978-1-4503-9660-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Yuka Sano, Ryohei Kobayashi, Norihisa Fujita, Taisuke Boku |
Performance Evaluation on GPU-FPGA Accelerated Computing Considering Interconnections between Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HEART ![In: HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9 - 10, 2022, pp. 10-16, 2022, ACM, 978-1-4503-9660-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Kosuke Tatsumura |
Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HEART ![In: HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Virtual Event, Germany, 21-23 June, 2021., pp. 1:1-1:6, 2021, ACM, 978-1-4503-8549-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | James Thomas 0003, Chris Lavin, Alireza Kaviani |
Software-like Compilation for Data Center FPGA Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HEART ![In: HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Virtual Event, Germany, 21-23 June, 2021., pp. 3:1-3:6, 2021, ACM, 978-1-4503-8549-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Ceren Çubukçu Cerasi |
Teknoloji girişimi hızlandırıcılarının incelenmesi ve etkinliklerinin araştırılması: Türkiye\'deki hızlandırıcıların ampirik bir analizi (Research of technology startup accelerators and their effectiveness: an empirical analysis of accelerators in Turkey) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2018 |
RDF |
|
23 | Kenji Kise |
Swap Based Merge Network for High Performance Sorting Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HEART ![In: Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018, Toronto, ON, Canada, June 20-22, 2018, pp. 8:1-8:7, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Ioannis Stamoulias, Matthias Möller, Rene Miedema, Christos Strydis, Christoforos Kachris, Dimitrios Soudris |
High-Performance Hardware Accelerators for Solving Ordinary Differential Equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HEART ![In: Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2017, Bochum, Germany, June 7-9, 2017, pp. 24:1-24:6, 2017, ACM, 978-1-4503-5316-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano |
Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HEART ![In: Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2017, Bochum, Germany, June 7-9, 2017, pp. 9:1-9:6, 2017, ACM, 978-1-4503-5316-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato |
Tightly Coupled Accelerators Architecture for Minimizing Communication Latency among Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, Cambridge, MA, USA, May 20-24, 2013, pp. 1030-1039, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
21 | John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel |
Cohesion: a hybrid memory model for accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 429-440, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
computer architecture, cache coherence, accelerator |
21 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil |
Synergistic execution of stream programs on multicores with accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 99-108, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CUDAa, partitioning, software pipelining, stream programming, GPU programming |
21 | Frederico Pratas, Leonel Sousa |
Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 237-246, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke |
Bridging the computation gap between programmable processors and hardwired accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 313-322, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | David M. Kunzman, Laxmikant V. Kalé |
Towards a framework for abstracting accelerators in parallel applications: experience with cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2009, November 14-20, 2009, Portland, Oregon, USA, 2009, ACM, 978-1-60558-744-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Gregorio Quintana-Ortí, Francisco D. Igual, Enrique S. Quintana-Ortí, Robert A. van de Geijn |
Solving dense linear systems on platforms with multiple hardware accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 121-130, 2009, ACM, 978-1-60558-397-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
algorithms-by-blocks, depencency analysis, dynamic scheduling, out-of-order execution, gpus |
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