Search results for "bit-adders"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
84	Seiji Kajihara, Tsutomu Sasao	On the Adders with Minimum Tests.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	ripple carry adder, minimum test set, test generation, stuck-at fault, carry look-ahead adders
81	Dilip P. Vasudevan, Parag K. Lala	A Technique for Modular Design of Self-Checking Carry-Select Adder.	DFT	2005	DBLP DOI BibTeX RDF
51	Johannes Grad, James E. Stine	Low power binary addition using carry increment adders.	ISCAS	2006	DBLP DOI BibTeX RDF
46	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis	Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.	ISVLSI	2004	DBLP DOI BibTeX RDF
44	Jong-Suk Lee, Dong Sam Ha	High Speed 1-bit Bypass Adder Design for Low Precision Additions.	ISCAS	2007	DBLP DOI BibTeX RDF
42	Ilya Obridko, Ran Ginosar	Minimal Energy Asynchronous Dynamic Adders.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
42	Radomir S. Stankovic, Jaakko Astola	Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams.	ISMVL	2002	DBLP DOI BibTeX RDF	Decision diagrams, Logic design, Switching functions, Spectral transforms
37	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
36	Massimo Alioto, Gaetano Palumbo	Analysis and comparison on full adder block in submicron technology.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
33	Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel	Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.	ASYNC	1997	DBLP DOI BibTeX RDF	completion detection, Brent-Kung, Carry-Bypass, asynchronous, adders, hazards, high-performance design
23	Sheng Sun, Larry McMurchie, Carl Sechen	A High-Performance 64-bit Adder Implemented in Output Prediction Logic.	ARVLSI	2001	DBLP DOI BibTeX RDF
22	M. Priyadharshni, Kishore Sanapala, Polinpapilinho F. Katina, K. Prasanna Kumar	Image analysis in healthcare systems using approximate multi-bit adders.	Int. J. Syst. Syst. Eng.	2023	DBLP DOI BibTeX RDF
22	Prasanna Kumar K., M. Priyadharshni, Kishore Sanapala, Polinpapilinho F. Katina	Image analysis in healthcare systems using approximate multi-bit adders.	Int. J. Syst. Syst. Eng.	2023	DBLP DOI BibTeX RDF
22	T. Suguna, M. Janaki Rani	Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications.	Int. J. Interact. Mob. Technol.	2020	DBLP DOI BibTeX RDF
22	Halil Kukner, Pieter Weckx, Sebastien Morrison, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken	NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes.	DSD	2014	DBLP DOI BibTeX RDF
22	Savithra Eratne, Claudia Romo, Eugene John	Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase.	CDES	2010	DBLP BibTeX RDF
21	Ge Yang 0004, Zhongda Wang, Sung-Mo Kang	Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
20	Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid	Residue to Binary Number Converters for (2n-1, 2n, 2n+1).	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	algorithm, adders, residue number system, circuit, arithmetic
17	Wolfgang Eppler, Thomas Fischer 0007, Hartmut Gemmeke, A. Menchikov	High Speed Neural Network Chip for Trigger Purposes in High Energy Physics.	DATE	1998	DBLP DOI BibTeX RDF	VME board with neural network chip SAND, Hardware accelerator for neural networks, High energy physics : trigger, on- and off-line analysis
15	Edgar Ferrer, Dorothy Bollman, Oscar Moreno	A Fast Finite Field Multiplier.	ARC	2007	DBLP DOI BibTeX RDF
15	Ahmad A. Hiasat	New Efficient Structure for a Modular Multiplier for RNS.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	hardware requirements, VLSI, computer arithmetic, Residue number system, time delay, modular multiplication
15	Henry Fuchs, Jack Goldfeather, Jeff P. Hultquist, Susan Spach, John D. Austin, Frederick P. Brooks Jr., John G. Eyles, John Poulton	Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes.	SIGGRAPH	1985	DBLP DOI BibTeX RDF
12	Sanza T. Kazadi, Yan Qi, Isaac Park, Nancy Huang, Paul Hwu, Brian Kwan, Waynn Lue, Hubert Li	Insufficiency Of Piecewise Evolution.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
12	Paliath Narendran, Jonathan Stillman	Formal Verification of the Sobel Image Processing Chip.	DAC	1988	DBLP BibTeX RDF