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Searching for blif with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1996-2013 (8)
Publication types (Num. hits)
inproceedings(8)
Venues (Conferences, Journals, ...)
CAV(1) ECBS(1) EDCC(1) FMCAD(1) FPGA(1) FPL(1) ISMVL(1) SBCCI(1)
Authors
Robert K. Brayton(3) Alan Mishchenko(2) Antônio Otávio Fernandes(1) Billy Chan(1) David A. Basin(1) Dennis Wu(1) Fabrício Vivas Andrade(1) Gurmeet Singh Manku(1) Jason Luu(1) Jerzy W. Greblicki(1) Jie-Hong Roland Jiang(1) Kevin Chung(1) Kevin E. Murray(1) Leandro Maia Silva(1) M. Gao(1) Mark Jarvin(1) More (+10 of total 31)
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Results
Found 8 publication records. Showing 8 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
117David A. Basin, Stefan Friedrich 0001, Sebastian Mödersheim B2M: A Semantic Based Tool for BLIF Hardware Descriptions. Search on Bibsonomy FMCAD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
49Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa Optimization of Multi-Valued Multi-Level Networks. Search on Bibsonomy ISMVL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
42Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz From Quartus to VPR: Converting HDL to BLIF with the Titan flow. Search on Bibsonomy FPL The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
36Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton SmartOpt: an industrial strength framework for logic synthesis. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF abc, blif, edge flow, smartopt, fpga, interface, technology mapping
25Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes BenCGen: a digital circuit generation tool for benchmarks. Search on Bibsonomy SBCCI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF benchmarks, sat solvers, combinational equivalence checking
25Jerzy W. Greblicki, Stanislaw J. Piestrak Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. Search on Bibsonomy EDCC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Gurmeet Singh Manku, Ramin Hojati, Robert K. Brayton Structural Symmetry and Model Checking. Search on Bibsonomy CAV The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Reinhard Bündgen, Wolfgang Küchlin, Werner Lauterbach Verification of the Sparrow Processor. Search on Bibsonomy ECBS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF symbolic hardware simulation, equational specifications, term rewriting, Hardware verification
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