Search results for "bsv"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
251	Gaurav Singh 0006, Sandeep K. Shukla	Verifying Compiler Based Refinement of BluespecTM.	SPIN	2008	DBLP DOI BibTeX RDF	Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker
146	Arvind, Rishiyur S. Nikhil	Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract).	MEMOCODE	2008	DBLP DOI BibTeX RDF
87	Gaurav Singh 0006, Sandeep K. Shukla	Model Checking Bluespec Specified Hardware Designs.	MTV	2007	DBLP DOI BibTeX RDF
77	Rishiyur S. Nikhil	Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design).	GPCE	2009	DBLP DOI BibTeX RDF	bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing
65	Flavius Gruian, Mark Westmijze	VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.	SAC	2008	DBLP DOI BibTeX RDF	embedded systems, java processor, Bluespec
65	Xinguo Yu, Hon Wai Leong, Changsheng Xu, Qi Tian 0002	Trajectory-Based Ball Detection and Tracking in Broadcast Soccer Video.	IEEE Trans. Multim.	2006	DBLP DOI BibTeX RDF
44	Flavius Gruian, Mark Westmijze	BlueJEP: a flexible and high-performance Java embedded processor.	JTRES	2007	DBLP DOI BibTeX RDF	embedded systems, Java processor, Bluespec
44	Flavius Gruian, Mark Westmijze	BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management.	SYNASC	2007	DBLP DOI BibTeX RDF
44	Nirav Dave, Michael Pellauer, S. Gerding, Arvind	802.11a transmitter: a case study in microarchitectural exploration.	MEMOCODE	2006	DBLP DOI BibTeX RDF
37	Nicholas Moore, Mark Lawford	A Case Study in the Automated Translation of BSV Hardware to PVS Formal Logic with Subsequent Verification.	TASE	2022	DBLP DOI BibTeX RDF
37	Yue Wang, Jiguo Yu, Biwei Yan, Guijuan Wang, Zhiguang Shan	BSV-PAGS: Blockchain-based special vehicles priority access guarantee scheme.	Comput. Commun.	2020	DBLP DOI BibTeX RDF
37	Hyoukjun Kwon, Tushar Krishna	OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel.	ISPASS	2017	DBLP DOI BibTeX RDF
37	Wei Zhang 0026, Yongjie Zhang 0003, Xiong Xiong, Xi Jin	Bsv Investors versus Rational Investors: an Agent-based Computational Finance Model.	Int. J. Inf. Technol. Decis. Mak.	2006	DBLP DOI BibTeX RDF
22	Daniel Gajski, Todd M. Austin, Steve Svoboda	What input-language is the best choice for high level synthesis (HLS)?	DAC	2010	DBLP DOI BibTeX RDF
22	Michal Karczmarek, Arvind	Synthesis from multi-cycle atomic actions as a solution to the timing closure problem.	ICCAD	2008	DBLP DOI BibTeX RDF
22	Nirav Dave, Man Cheuk Ng, Arvind	Automatic synthesis of cache-coherence protocol processors using Bluespec.	MEMOCODE	2005	DBLP DOI BibTeX RDF