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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 17 occurrences of 14 keywords
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Results
Found 16 publication records. Showing 16 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
251 | Gaurav Singh 0006, Sandeep K. Shukla |
Verifying Compiler Based Refinement of BluespecTM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 15th International SPIN Workshop, Los Angeles, CA, USA, August 10-12, 2008, Proceedings, pp. 250-269, 2008, Springer, 978-3-540-85113-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker |
146 | Arvind, Rishiyur S. Nikhil |
Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), June 5-7, 2008, Anaheim, CA, USA, pp. 205-206, 2008, IEEE Computer Society, 978-1-4244-2417-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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87 | Gaurav Singh 0006, Sandeep K. Shukla |
Model Checking Bluespec Specified Hardware Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA, pp. 39-43, 2007, IEEE Computer Society, 978-0-7695-3241-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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77 | Rishiyur S. Nikhil |
Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design). ![Search on Bibsonomy](Pics/bibsonomy.png) |
GPCE ![In: Generative Programming and Component Engineering, 8th International Conference, GPCE 2009, Denver, Colorado, USA, October 4-5, 2009, Proceedings, pp. 1-2, 2009, ACM, 978-1-60558-494-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing |
65 | Flavius Gruian, Mark Westmijze |
VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 1492-1497, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
embedded systems, java processor, Bluespec |
65 | Xinguo Yu, Hon Wai Leong, Changsheng Xu, Qi Tian 0002 |
Trajectory-Based Ball Detection and Tracking in Broadcast Soccer Video. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multim. ![In: IEEE Trans. Multim. 8(6), pp. 1164-1178, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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44 | Flavius Gruian, Mark Westmijze |
BlueJEP: a flexible and high-performance Java embedded processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: Proceedings of the 5th International Workshop on Java Technologies for Real-time and Embedded Systems, JTRES 2007, Institute of Computer Engineering, Vienna University of Technology, 26-28 September 2007, Vienna, Austria, pp. 222-229, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded systems, Java processor, Bluespec |
44 | Flavius Gruian, Mark Westmijze |
BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYNASC ![In: Proceedings of the Ninth International Symposium on Symbolic and Numeric Algorithms for Scientific Computing, SYNASC 2007, Timisoara, Romania, September 26-29, 2007, pp. 459-466, 2007, IEEE Computer Society, 978-0-7695-3078-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Nirav Dave, Michael Pellauer, S. Gerding, Arvind |
802.11a transmitter: a case study in microarchitectural exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 27-29 July 2006, Embassy Suites, Napa, California, USA, pp. 59-68, 2006, IEEE Computer Society, 1-4244-0421-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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37 | Nicholas Moore, Mark Lawford |
A Case Study in the Automated Translation of BSV Hardware to PVS Formal Logic with Subsequent Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TASE ![In: Theoretical Aspects of Software Engineering - 16th International Symposium, TASE 2022, Cluj-Napoca, Romania, July 8-10, 2022, Proceedings, pp. 65-72, 2022, Springer, 978-3-031-10362-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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37 | Yue Wang, Jiguo Yu, Biwei Yan, Guijuan Wang, Zhiguang Shan |
BSV-PAGS: Blockchain-based special vehicles priority access guarantee scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Commun. ![In: Comput. Commun. 161, pp. 28-40, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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37 | Hyoukjun Kwon, Tushar Krishna |
OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017, pp. 195-204, 2017, IEEE Computer Society, 978-1-5386-3890-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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37 | Wei Zhang 0026, Yongjie Zhang 0003, Xiong Xiong, Xi Jin |
Bsv Investors versus Rational Investors: an Agent-based Computational Finance Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Inf. Technol. Decis. Mak. ![In: Int. J. Inf. Technol. Decis. Mak. 5(3), pp. 455-466, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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22 | Daniel Gajski, Todd M. Austin, Steve Svoboda |
What input-language is the best choice for high level synthesis (HLS)? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 857-858, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Michal Karczmarek, Arvind |
Synthesis from multi-cycle atomic actions as a solution to the timing closure problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 24-31, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Nirav Dave, Man Cheuk Ng, Arvind |
Automatic synthesis of cache-coherence protocol processors using Bluespec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 11-14 July 2005, Verona, Italy, Proceedings, pp. 25-34, 2005, IEEE Computer Society, 0-7803-9227-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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